[PATCH 1/4] phy: mediatek: phy-mtk-hdmi: Switch to regmap for mmio access

[PATCH 1/4] phy: mediatek: phy-mtk-hdmi: Switch to regmap for mmio access

[AngeloGioacchino Del Regno]

Switch to using the generic regmap API instead of calls to readl/writel
for MMIO register access, removing custom crafted update/set/clear_bits
functions and also allowing us to reduce code size.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c | 165 ++++++++++-----------
 drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c | 126 ++++++++--------
 drivers/phy/mediatek/phy-mtk-hdmi.c        |  51 ++-----
 drivers/phy/mediatek/phy-mtk-hdmi.h        |   9 +-
 4 files changed, 158 insertions(+), 193 deletions(-)

diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
index b74c65a1762c..09e0dd7499d8 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
@@ -69,19 +69,19 @@ static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
 {
 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
 
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON7, RG_HTPLL_AUTOK_EN);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_RLH_EN);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_EN_MBIAS);
 	usleep_range(80, 100);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_EN);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
 	usleep_range(80, 100);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
 	usleep_range(80, 100);
 	return 0;
 }
@@ -90,19 +90,19 @@ static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
 {
 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
 
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
 	usleep_range(80, 100);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_EN);
 	usleep_range(80, 100);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_EN_MBIAS);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_RLH_EN);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON7, RG_HTPLL_AUTOK_EN);
 	usleep_range(80, 100);
 }
 
@@ -125,37 +125,34 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 	else
 		pos_div = 1;
 
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),
-			  RG_HTPLL_IC_MASK);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
-			  RG_HTPLL_IR_MASK);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV),
-			  RG_HDMITX_TX_POSDIV_MASK);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL),
-			  RG_HTPLL_FBKSEL_MASK);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV),
-			  RG_HTPLL_FBKDIV_MASK);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN),
-			  RG_HTPLL_DIVEN_MASK);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP),
-			  RG_HTPLL_BP_MASK);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC),
-			  RG_HTPLL_BC_MASK);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR),
-			  RG_HTPLL_BR_MASK);
-
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PRED_IMP);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS),
-			  RG_HDMITX_PRED_IBIAS_MASK);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_IMP_MASK);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP),
-			  RG_HDMITX_DRV_IMP_MASK);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, (0xa << RG_HDMITX_DRV_IBIAS),
-			  RG_HDMITX_DRV_IBIAS_MASK);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_PREDIV_MASK);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_IC_MASK, BIT(RG_HTPLL_IC));
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_IR_MASK, BIT(RG_HTPLL_IR));
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_TX_POSDIV_MASK,
+			   (pos_div << RG_HDMITX_TX_POSDIV));
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_FBKSEL_MASK,
+			   (1 << RG_HTPLL_FBKSEL));
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_FBKDIV_MASK,
+			   (19 << RG_HTPLL_FBKDIV));
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON7, RG_HTPLL_DIVEN_MASK,
+			   (0x2 << RG_HTPLL_DIVEN));
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_BP_MASK,
+			   (0xc << RG_HTPLL_BP));
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_BC_MASK,
+			   (0x2 << RG_HTPLL_BC));
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_BR_MASK, BIT(RG_HTPLL_BR));
+
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PRED_IMP);
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PRED_IBIAS_MASK,
+			   (0x3 << RG_HDMITX_PRED_IBIAS));
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_IMP_MASK);
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_DRV_IMP_MASK,
+			   (0x28 << RG_HDMITX_DRV_IMP));
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON4, RG_HDMITX_RESERVE_MASK, 0x28);
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_DRV_IBIAS_MASK,
+			   (0xa << RG_HDMITX_DRV_IBIAS));
 	return 0;
 }
 
@@ -163,10 +160,11 @@ static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
 					      unsigned long parent_rate)
 {
 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
-	unsigned long out_rate, val;
+	unsigned long out_rate;
+	u32 val;
 
-	val = (readl(hdmi_phy->regs + HDMI_CON6)
-	       & RG_HTPLL_PREDIV_MASK) >> RG_HTPLL_PREDIV;
+	regmap_read(hdmi_phy->regmap, HDMI_CON6, &val);
+	val = (val & RG_HTPLL_PREDIV_MASK) >> RG_HTPLL_PREDIV;
 	switch (val) {
 	case 0x00:
 		out_rate = parent_rate;
@@ -179,14 +177,15 @@ static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
 		break;
 	}
 
-	val = (readl(hdmi_phy->regs + HDMI_CON6)
-	       & RG_HTPLL_FBKDIV_MASK) >> RG_HTPLL_FBKDIV;
+	regmap_read(hdmi_phy->regmap, HDMI_CON6, &val);
+	val = (val & RG_HTPLL_FBKDIV_MASK) >> RG_HTPLL_FBKDIV;
 	out_rate *= (val + 1) * 2;
-	val = (readl(hdmi_phy->regs + HDMI_CON2)
-	       & RG_HDMITX_TX_POSDIV_MASK);
+	regmap_read(hdmi_phy->regmap, HDMI_CON2, &val);
+	val &= RG_HDMITX_TX_POSDIV_MASK;
 	out_rate >>= (val >> RG_HDMITX_TX_POSDIV);
 
-	if (readl(hdmi_phy->regs + HDMI_CON2) & RG_HDMITX_EN_TX_POSDIV)
+	regmap_read(hdmi_phy->regmap, HDMI_CON2, &val);
+	if (val & RG_HDMITX_EN_TX_POSDIV)
 		out_rate /= 5;
 
 	return out_rate;
@@ -202,37 +201,37 @@ static const struct clk_ops mtk_hdmi_phy_pll_ops = {
 
 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
 {
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON7, RG_HTPLL_AUTOK_EN);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_RLH_EN);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_EN_MBIAS);
 	usleep_range(80, 100);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_EN);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
 	usleep_range(80, 100);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
 	usleep_range(80, 100);
 }
 
 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
 {
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
 	usleep_range(80, 100);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_EN);
 	usleep_range(80, 100);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_EN_MBIAS);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_RLH_EN);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON7, RG_HTPLL_AUTOK_EN);
 	usleep_range(80, 100);
 }
 
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
index 6cdfdf5a698a..e317bf4a9db9 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
@@ -111,15 +111,15 @@ static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
 {
 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
 
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON3, RG_HDMITX_MHLCK_EN);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
 	usleep_range(100, 150);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_PLL_EN);
 	usleep_range(100, 150);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
 
 	return 0;
 }
@@ -128,14 +128,14 @@ static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
 {
 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
 
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
 	usleep_range(100, 150);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_PLL_EN);
 	usleep_range(100, 150);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
 	usleep_range(100, 150);
 }
 
@@ -177,65 +177,59 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 		div = 1;
 	}
 
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
-			  (pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV);
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
-			  (0x1 << PLL_IC_SHIFT) | (0x1 << PLL_IR_SHIFT),
-			  RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
-			  (div << PLL_TXDIV_SHIFT), RG_HDMITX_PLL_TXDIV);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
-			  (0x1 << PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT),
-			  RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
-			  (0x2 << PLL_DIVEN_SHIFT), RG_HDMITX_PLL_DIVEN);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
-			  (0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) |
-			  (0x1 << PLL_BR_SHIFT),
-			  RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
-			  RG_HDMITX_PLL_BR);
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_PLL_PREDIV,
+			   (pre_div << PREDIV_SHIFT));
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON0,
+			   RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR,
+			   BIT(PLL_IC_SHIFT) | BIT(PLL_IR_SHIFT));
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_TXDIV,
+			   (div << PLL_TXDIV_SHIFT));
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON0,
+			   RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV,
+			  BIT(PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT));
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_DIVEN,
+			   (0x2 << PLL_DIVEN_SHIFT));
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON0,
+			   RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC | RG_HDMITX_PLL_BR,
+			   (0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) |
+			   (0x1 << PLL_BR_SHIFT));
 	if (rate < 165000000) {
-		mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
+		regmap_clear_bits(hdmi_phy->regmap, HDMI_CON3,
 					RG_HDMITX_PRD_IMP_EN);
 		pre_ibias = 0x3;
 		imp_en = 0x0;
 		hdmi_ibias = hdmi_phy->ibias;
 	} else {
-		mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
+		regmap_set_bits(hdmi_phy->regmap, HDMI_CON3,
 				      RG_HDMITX_PRD_IMP_EN);
 		pre_ibias = 0x6;
 		imp_en = 0xf;
 		hdmi_ibias = hdmi_phy->ibias_up;
 	}
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
-			  (pre_ibias << PRD_IBIAS_CLK_SHIFT) |
-			  (pre_ibias << PRD_IBIAS_D2_SHIFT) |
-			  (pre_ibias << PRD_IBIAS_D1_SHIFT) |
-			  (pre_ibias << PRD_IBIAS_D0_SHIFT),
-			  RG_HDMITX_PRD_IBIAS_CLK |
-			  RG_HDMITX_PRD_IBIAS_D2 |
-			  RG_HDMITX_PRD_IBIAS_D1 |
-			  RG_HDMITX_PRD_IBIAS_D0);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
-			  (imp_en << DRV_IMP_EN_SHIFT),
-			  RG_HDMITX_DRV_IMP_EN);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
-			  (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
-			  (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
-			  (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
-			  (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
-			  RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
-			  RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
-			  (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) |
-			  (hdmi_ibias << DRV_IBIAS_D2_SHIFT) |
-			  (hdmi_ibias << DRV_IBIAS_D1_SHIFT) |
-			  (hdmi_ibias << DRV_IBIAS_D0_SHIFT),
-			  RG_HDMITX_DRV_IBIAS_CLK |
-			  RG_HDMITX_DRV_IBIAS_D2 |
-			  RG_HDMITX_DRV_IBIAS_D1 |
-			  RG_HDMITX_DRV_IBIAS_D0);
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON4,
+			   RG_HDMITX_PRD_IBIAS_CLK | RG_HDMITX_PRD_IBIAS_D2 |
+			   RG_HDMITX_PRD_IBIAS_D1 | RG_HDMITX_PRD_IBIAS_D0,
+			   (pre_ibias << PRD_IBIAS_CLK_SHIFT) |
+			   (pre_ibias << PRD_IBIAS_D2_SHIFT) |
+			   (pre_ibias << PRD_IBIAS_D1_SHIFT) |
+			   (pre_ibias << PRD_IBIAS_D0_SHIFT));
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON3, RG_HDMITX_DRV_IMP_EN,
+			   (imp_en << DRV_IMP_EN_SHIFT));
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON6,
+			   RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
+			   RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0,
+			   (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
+			   (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
+			   (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
+			   (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT));
+	regmap_update_bits(hdmi_phy->regmap, HDMI_CON5,
+			   RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 |
+			   RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0,
+			   (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) |
+			   (hdmi_ibias << DRV_IBIAS_D2_SHIFT) |
+			   (hdmi_ibias << DRV_IBIAS_D1_SHIFT) |
+			   (hdmi_ibias << DRV_IBIAS_D0_SHIFT));
 	return 0;
 }
 
@@ -257,17 +251,15 @@ static const struct clk_ops mtk_hdmi_phy_pll_ops = {
 
 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
 {
-	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
-			      RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN |
-			      RG_HDMITX_DRV_EN);
+	regmap_set_bits(hdmi_phy->regmap, HDMI_CON3,
+			RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN | RG_HDMITX_DRV_EN);
 	usleep_range(100, 150);
 }
 
 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
 {
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
-				RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN |
-				RG_HDMITX_SER_EN);
+	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON3,
+			  RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN | RG_HDMITX_SER_EN);
 }
 
 struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c b/drivers/phy/mediatek/phy-mtk-hdmi.c
index 5fb4217fb8e0..707e90691e6e 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi.c
@@ -15,39 +15,6 @@ static const struct phy_ops mtk_hdmi_phy_dev_ops = {
 	.owner = THIS_MODULE,
 };
 
-void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
-			     u32 bits)
-{
-	void __iomem *reg = hdmi_phy->regs + offset;
-	u32 tmp;
-
-	tmp = readl(reg);
-	tmp &= ~bits;
-	writel(tmp, reg);
-}
-
-void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
-			   u32 bits)
-{
-	void __iomem *reg = hdmi_phy->regs + offset;
-	u32 tmp;
-
-	tmp = readl(reg);
-	tmp |= bits;
-	writel(tmp, reg);
-}
-
-void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
-		       u32 val, u32 mask)
-{
-	void __iomem *reg = hdmi_phy->regs + offset;
-	u32 tmp;
-
-	tmp = readl(reg);
-	tmp = (tmp & ~mask) | (val & mask);
-	writel(tmp, reg);
-}
-
 inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
 {
 	return container_of(hw, struct mtk_hdmi_phy, pll_hw);
@@ -96,6 +63,13 @@ static void mtk_hdmi_phy_clk_get_data(struct mtk_hdmi_phy *hdmi_phy,
 	clk_init->ops = hdmi_phy->conf->hdmi_phy_clk_ops;
 }
 
+static const struct regmap_config mtk_hdmi_phy_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.disable_locking = true,
+};
+
 static int mtk_hdmi_phy_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -109,15 +83,20 @@ static int mtk_hdmi_phy_probe(struct platform_device *pdev)
 
 	struct phy *phy;
 	struct phy_provider *phy_provider;
+	void __iomem *regs;
 	int ret;
 
 	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
 	if (!hdmi_phy)
 		return -ENOMEM;
 
-	hdmi_phy->regs = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(hdmi_phy->regs))
-		return PTR_ERR(hdmi_phy->regs);
+	regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(regs))
+		return PTR_ERR(regs);
+
+	hdmi_phy->regmap = devm_regmap_init_mmio(dev, regs, &mtk_hdmi_phy_regmap_config);
+	if (IS_ERR(hdmi_phy->regmap))
+		return PTR_ERR(hdmi_phy->regmap);
 
 	ref_clk = devm_clk_get(dev, "pll_ref");
 	if (IS_ERR(ref_clk)) {
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.h b/drivers/phy/mediatek/phy-mtk-hdmi.h
index dcf9bb13699b..a0571271d730 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi.h
+++ b/drivers/phy/mediatek/phy-mtk-hdmi.h
@@ -15,6 +15,7 @@
 #include <linux/of_device.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
+#include <linux/regmap.h>
 #include <linux/types.h>
 
 struct mtk_hdmi_phy;
@@ -28,7 +29,7 @@ struct mtk_hdmi_phy_conf {
 };
 
 struct mtk_hdmi_phy {
-	void __iomem *regs;
+	struct regmap *regmap;
 	struct device *dev;
 	struct mtk_hdmi_phy_conf *conf;
 	struct clk *pll;
@@ -42,12 +43,6 @@ struct mtk_hdmi_phy {
 	unsigned int ibias_up;
 };
 
-void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
-			     u32 bits);
-void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
-			   u32 bits);
-void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
-		       u32 val, u32 mask);
 struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
 
 extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
-- 
2.33.1

[PATCH 2/4] phy: mediatek: phy-mtk-hdmi: Reorder to remove forward declarations

[AngeloGioacchino Del Regno]

Forward declarations for mtk_hdmi_power_{on,off} aren't necessary:
move mtk_hdmi_phy_dev_ops down to remove forward declarations.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/phy/mediatek/phy-mtk-hdmi.c | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c b/drivers/phy/mediatek/phy-mtk-hdmi.c
index 707e90691e6e..b4193cb4e4e3 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi.c
@@ -6,15 +6,6 @@
 
 #include "phy-mtk-hdmi.h"
 
-static int mtk_hdmi_phy_power_on(struct phy *phy);
-static int mtk_hdmi_phy_power_off(struct phy *phy);
-
-static const struct phy_ops mtk_hdmi_phy_dev_ops = {
-	.power_on = mtk_hdmi_phy_power_on,
-	.power_off = mtk_hdmi_phy_power_off,
-	.owner = THIS_MODULE,
-};
-
 inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
 {
 	return container_of(hw, struct mtk_hdmi_phy, pll_hw);
@@ -43,6 +34,12 @@ static int mtk_hdmi_phy_power_off(struct phy *phy)
 	return 0;
 }
 
+static const struct phy_ops mtk_hdmi_phy_dev_ops = {
+	.power_on = mtk_hdmi_phy_power_on,
+	.power_off = mtk_hdmi_phy_power_off,
+	.owner = THIS_MODULE,
+};
+
 static const struct phy_ops *
 mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
 {
-- 
2.33.1

Re: [PATCH 2/4] phy: mediatek: phy-mtk-hdmi: Reorder to remove forward declarations

[Chunfeng Yun]

On Mon, 2022-01-03 at 16:30 +0100, AngeloGioacchino Del Regno wrote:
> Forward declarations for mtk_hdmi_power_{on,off} aren't necessary:
> move mtk_hdmi_phy_dev_ops down to remove forward declarations.
> 
> Signed-off-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
>  drivers/phy/mediatek/phy-mtk-hdmi.c | 15 ++++++---------
>  1 file changed, 6 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c
> b/drivers/phy/mediatek/phy-mtk-hdmi.c
> index 707e90691e6e..b4193cb4e4e3 100644
> --- a/drivers/phy/mediatek/phy-mtk-hdmi.c
> +++ b/drivers/phy/mediatek/phy-mtk-hdmi.c
> @@ -6,15 +6,6 @@
>  
>  #include "phy-mtk-hdmi.h"
>  
> -static int mtk_hdmi_phy_power_on(struct phy *phy);
> -static int mtk_hdmi_phy_power_off(struct phy *phy);
> -
> -static const struct phy_ops mtk_hdmi_phy_dev_ops = {
> -	.power_on = mtk_hdmi_phy_power_on,
> -	.power_off = mtk_hdmi_phy_power_off,
> -	.owner = THIS_MODULE,
> -};
> -
>  inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
>  {
>  	return container_of(hw, struct mtk_hdmi_phy, pll_hw);
> @@ -43,6 +34,12 @@ static int mtk_hdmi_phy_power_off(struct phy *phy)
>  	return 0;
>  }
>  
> +static const struct phy_ops mtk_hdmi_phy_dev_ops = {
> +	.power_on = mtk_hdmi_phy_power_on,
> +	.power_off = mtk_hdmi_phy_power_off,
> +	.owner = THIS_MODULE,
> +};
> +
>  static const struct phy_ops *
>  mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
>  {
Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>

Thanks a lot

[PATCH 3/4] phy: mediatek: phy-mtk-hdmi: Reorder and stop implicit header inclusion

[AngeloGioacchino Del Regno]

All the headers for phy-mtk-{hdmi,hdmi-mt2701,hdmi-mt8183}.c were
included from phy-mtk-mipi-dsi.h, but this isn't optimal: in order to
increase readability and sensibly reduce build times, the inclusions
should be done per-file, also avoiding to include unused headers and
should not be implicit.

For this reason, move the inclusions to each file and remove unused ones.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c |  5 +++++
 drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c |  5 +++++
 drivers/phy/mediatek/phy-mtk-hdmi.c        |  8 ++++++++
 drivers/phy/mediatek/phy-mtk-hdmi.h        | 10 +---------
 4 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
index 09e0dd7499d8..270c5f538483 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
@@ -4,6 +4,11 @@
  * Author: Chunhui Dai <chunhui.dai@mediatek.com>
  */
 
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
 #include "phy-mtk-hdmi.h"
 
 #define HDMI_CON0	0x00
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
index e317bf4a9db9..87ba9a3687b7 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
@@ -4,6 +4,11 @@
  * Author: Jie Qiu <jie.qiu@mediatek.com>
  */
 
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
 #include "phy-mtk-hdmi.h"
 
 #define HDMI_CON0		0x00
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c b/drivers/phy/mediatek/phy-mtk-hdmi.c
index b4193cb4e4e3..e037fa89696c 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi.c
@@ -4,6 +4,14 @@
  * Author: Jie Qiu <jie.qiu@mediatek.com>
  */
 
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/phy/phy.h>
 #include "phy-mtk-hdmi.h"
 
 inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.h b/drivers/phy/mediatek/phy-mtk-hdmi.h
index a0571271d730..ef81e44a235d 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi.h
+++ b/drivers/phy/mediatek/phy-mtk-hdmi.h
@@ -6,17 +6,9 @@
 
 #ifndef _MTK_HDMI_PHY_H
 #define _MTK_HDMI_PHY_H
-#include <linux/clk.h>
+
 #include <linux/clk-provider.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/mfd/syscon.h>
-#include <linux/module.h>
-#include <linux/of_device.h>
-#include <linux/phy/phy.h>
-#include <linux/platform_device.h>
 #include <linux/regmap.h>
-#include <linux/types.h>
 
 struct mtk_hdmi_phy;
 
-- 
2.33.1

Re: [PATCH 3/4] phy: mediatek: phy-mtk-hdmi: Reorder and stop implicit header inclusion

[Chunfeng Yun]

On Mon, 2022-01-03 at 16:30 +0100, AngeloGioacchino Del Regno wrote:
> All the headers for phy-mtk-{hdmi,hdmi-mt2701,hdmi-mt8183}.c were
> included from phy-mtk-mipi-dsi.h, but this isn't optimal: in order to
> increase readability and sensibly reduce build times, the inclusions
> should be done per-file, also avoiding to include unused headers and
> should not be implicit.
> 
> For this reason, move the inclusions to each file and remove unused
> ones.
> 
> Signed-off-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
>  drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c |  5 +++++
>  drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c |  5 +++++
>  drivers/phy/mediatek/phy-mtk-hdmi.c        |  8 ++++++++
>  drivers/phy/mediatek/phy-mtk-hdmi.h        | 10 +---------
>  4 files changed, 19 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
> b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
> index 09e0dd7499d8..270c5f538483 100644
> --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
> +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
> @@ -4,6 +4,11 @@
>   * Author: Chunhui Dai <chunhui.dai@mediatek.com>
>   */
>  
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/module.h>
> +#include <linux/regmap.h>
>  #include "phy-mtk-hdmi.h"
>  
>  #define HDMI_CON0	0x00
> diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
> b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
> index e317bf4a9db9..87ba9a3687b7 100644
> --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
> +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
> @@ -4,6 +4,11 @@
>   * Author: Jie Qiu <jie.qiu@mediatek.com>
>   */
>  
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/module.h>
> +#include <linux/regmap.h>
>  #include "phy-mtk-hdmi.h"
>  
>  #define HDMI_CON0		0x00
> diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c
> b/drivers/phy/mediatek/phy-mtk-hdmi.c
> index b4193cb4e4e3..e037fa89696c 100644
> --- a/drivers/phy/mediatek/phy-mtk-hdmi.c
> +++ b/drivers/phy/mediatek/phy-mtk-hdmi.c
> @@ -4,6 +4,14 @@
>   * Author: Jie Qiu <jie.qiu@mediatek.com>
>   */
>  
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/device.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/phy/phy.h>
>  #include "phy-mtk-hdmi.h"
>  
>  inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
> diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.h
> b/drivers/phy/mediatek/phy-mtk-hdmi.h
> index a0571271d730..ef81e44a235d 100644
> --- a/drivers/phy/mediatek/phy-mtk-hdmi.h
> +++ b/drivers/phy/mediatek/phy-mtk-hdmi.h
> @@ -6,17 +6,9 @@
>  
>  #ifndef _MTK_HDMI_PHY_H
>  #define _MTK_HDMI_PHY_H
> -#include <linux/clk.h>
> +
>  #include <linux/clk-provider.h>
> -#include <linux/delay.h>
> -#include <linux/io.h>
> -#include <linux/mfd/syscon.h>
> -#include <linux/module.h>
> -#include <linux/of_device.h>
> -#include <linux/phy/phy.h>
> -#include <linux/platform_device.h>
>  #include <linux/regmap.h>
> -#include <linux/types.h>
Please do not move common headers also into .c files

>  
>  struct mtk_hdmi_phy;
>  

[PATCH 4/4] phy: mediatek: phy-mtk-hdmi: Simplify with dev_err_probe()

[AngeloGioacchino Del Regno]

Use the dev_err_probe() helper to simplify error handling during probe.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/phy/mediatek/phy-mtk-hdmi.c | 50 +++++++++++------------------
 1 file changed, 19 insertions(+), 31 deletions(-)

diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c b/drivers/phy/mediatek/phy-mtk-hdmi.c
index e037fa89696c..4f40a6eea004 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi.c
@@ -104,20 +104,16 @@ static int mtk_hdmi_phy_probe(struct platform_device *pdev)
 		return PTR_ERR(hdmi_phy->regmap);
 
 	ref_clk = devm_clk_get(dev, "pll_ref");
-	if (IS_ERR(ref_clk)) {
-		ret = PTR_ERR(ref_clk);
-		dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
-			ret);
-		return ret;
-	}
+	if (IS_ERR(ref_clk))
+		return dev_err_probe(dev, PTR_ERR(ref_clk),
+				     "Failed to get PLL reference clock\n");
+
 	ref_clk_name = __clk_get_name(ref_clk);
 
 	ret = of_property_read_string(dev->of_node, "clock-output-names",
 				      &clk_init.name);
-	if (ret < 0) {
-		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
-		return ret;
-	}
+	if (ret < 0)
+		return dev_err_probe(dev, ret, "Failed to read clock-output-names\n");
 
 	hdmi_phy->dev = dev;
 	hdmi_phy->conf =
@@ -125,25 +121,19 @@ static int mtk_hdmi_phy_probe(struct platform_device *pdev)
 	mtk_hdmi_phy_clk_get_data(hdmi_phy, &clk_init);
 	hdmi_phy->pll_hw.init = &clk_init;
 	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
-	if (IS_ERR(hdmi_phy->pll)) {
-		ret = PTR_ERR(hdmi_phy->pll);
-		dev_err(dev, "Failed to register PLL: %d\n", ret);
-		return ret;
-	}
+	if (IS_ERR(hdmi_phy->pll))
+		return dev_err_probe(dev, PTR_ERR(hdmi_phy->pll),
+				    "Failed to register PLL\n");
 
 	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
 				   &hdmi_phy->ibias);
-	if (ret < 0) {
-		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
-		return ret;
-	}
+	if (ret < 0)
+		return dev_err_probe(dev, ret, "Failed to get ibias\n");
 
 	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
 				   &hdmi_phy->ibias_up);
-	if (ret < 0) {
-		dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
-		return ret;
-	}
+	if (ret < 0)
+		return dev_err_probe(dev, ret, "Failed to get ibias_up\n");
 
 	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
 	hdmi_phy->drv_imp_clk = 0x30;
@@ -152,17 +142,15 @@ static int mtk_hdmi_phy_probe(struct platform_device *pdev)
 	hdmi_phy->drv_imp_d0 = 0x30;
 
 	phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
-	if (IS_ERR(phy)) {
-		dev_err(dev, "Failed to create HDMI PHY\n");
-		return PTR_ERR(phy);
-	}
+	if (IS_ERR(phy))
+		return dev_err_probe(dev, PTR_ERR(phy), "Cannot create HDMI PHY\n");
+
 	phy_set_drvdata(phy, hdmi_phy);
 
 	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-	if (IS_ERR(phy_provider)) {
-		dev_err(dev, "Failed to register HDMI PHY\n");
-		return PTR_ERR(phy_provider);
-	}
+	if (IS_ERR(phy_provider))
+		return dev_err_probe(dev, PTR_ERR(phy_provider),
+				     "Failed to register HDMI PHY\n");
 
 	if (hdmi_phy->conf->pll_default_off)
 		hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
-- 
2.33.1

Re: [PATCH 4/4] phy: mediatek: phy-mtk-hdmi: Simplify with dev_err_probe()

[Chunfeng Yun]

On Mon, 2022-01-03 at 16:30 +0100, AngeloGioacchino Del Regno wrote:
> Use the dev_err_probe() helper to simplify error handling during
> probe.
> 
> Signed-off-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
>  drivers/phy/mediatek/phy-mtk-hdmi.c | 50 +++++++++++--------------
> ----
>  1 file changed, 19 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c
> b/drivers/phy/mediatek/phy-mtk-hdmi.c
> index e037fa89696c..4f40a6eea004 100644
> --- a/drivers/phy/mediatek/phy-mtk-hdmi.c
> +++ b/drivers/phy/mediatek/phy-mtk-hdmi.c
> @@ -104,20 +104,16 @@ static int mtk_hdmi_phy_probe(struct
> platform_device *pdev)
>  		return PTR_ERR(hdmi_phy->regmap);
>  
>  	ref_clk = devm_clk_get(dev, "pll_ref");
> -	if (IS_ERR(ref_clk)) {
> -		ret = PTR_ERR(ref_clk);
> -		dev_err(&pdev->dev, "Failed to get PLL reference clock:
> %d\n",
> -			ret);
> -		return ret;
> -	}
> +	if (IS_ERR(ref_clk))
> +		return dev_err_probe(dev, PTR_ERR(ref_clk),
> +				     "Failed to get PLL reference
> clock\n");
> +
>  	ref_clk_name = __clk_get_name(ref_clk);
>  
>  	ret = of_property_read_string(dev->of_node, "clock-output-
> names",
>  				      &clk_init.name);
> -	if (ret < 0) {
> -		dev_err(dev, "Failed to read clock-output-names: %d\n",
> ret);
> -		return ret;
> -	}
> +	if (ret < 0)
> +		return dev_err_probe(dev, ret, "Failed to read clock-
> output-names\n");
Seems no need change it if no EPROBE_DEFER happens

>  
>  	hdmi_phy->dev = dev;
>  	hdmi_phy->conf =
> @@ -125,25 +121,19 @@ static int mtk_hdmi_phy_probe(struct
> platform_device *pdev)
>  	mtk_hdmi_phy_clk_get_data(hdmi_phy, &clk_init);
>  	hdmi_phy->pll_hw.init = &clk_init;
>  	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
> -	if (IS_ERR(hdmi_phy->pll)) {
> -		ret = PTR_ERR(hdmi_phy->pll);
> -		dev_err(dev, "Failed to register PLL: %d\n", ret);
> -		return ret;
> -	}
> +	if (IS_ERR(hdmi_phy->pll))
> +		return dev_err_probe(dev, PTR_ERR(hdmi_phy->pll),
> +				    "Failed to register PLL\n");
>  
>  	ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
>  				   &hdmi_phy->ibias);
> -	if (ret < 0) {
> -		dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
> -		return ret;
> -	}
> +	if (ret < 0)
> +		return dev_err_probe(dev, ret, "Failed to get
> ibias\n");
ditto

Thanks
>  
>  	ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
>  				   &hdmi_phy->ibias_up);
> -	if (ret < 0) {
> -		dev_err(&pdev->dev, "Failed to get ibias up: %d\n",
> ret);
> -		return ret;
> -	}
> +	if (ret < 0)
> +		return dev_err_probe(dev, ret, "Failed to get
> ibias_up\n");
>  
>  	dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
>  	hdmi_phy->drv_imp_clk = 0x30;
> @@ -152,17 +142,15 @@ static int mtk_hdmi_phy_probe(struct
> platform_device *pdev)
>  	hdmi_phy->drv_imp_d0 = 0x30;
>  
>  	phy = devm_phy_create(dev, NULL,
> mtk_hdmi_phy_dev_get_ops(hdmi_phy));
> -	if (IS_ERR(phy)) {
> -		dev_err(dev, "Failed to create HDMI PHY\n");
> -		return PTR_ERR(phy);
> -	}
> +	if (IS_ERR(phy))
> +		return dev_err_probe(dev, PTR_ERR(phy), "Cannot create
> HDMI PHY\n");
> +
>  	phy_set_drvdata(phy, hdmi_phy);
>  
>  	phy_provider = devm_of_phy_provider_register(dev,
> of_phy_simple_xlate);
> -	if (IS_ERR(phy_provider)) {
> -		dev_err(dev, "Failed to register HDMI PHY\n");
> -		return PTR_ERR(phy_provider);
> -	}
> +	if (IS_ERR(phy_provider))
> +		return dev_err_probe(dev, PTR_ERR(phy_provider),
> +				     "Failed to register HDMI PHY\n");
>  
>  	if (hdmi_phy->conf->pll_default_off)
>  		hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);

Re: [PATCH 1/4] phy: mediatek: phy-mtk-hdmi: Switch to regmap for mmio access

[Chunfeng Yun]

On Mon, 2022-01-03 at 16:30 +0100, AngeloGioacchino Del Regno wrote:
> Switch to using the generic regmap API instead of calls to
> readl/writel
> for MMIO register access, removing custom crafted
> update/set/clear_bits
> functions and also allowing us to reduce code size.
Using readl/writel is simpler than regmap here

Thanks

> 
> Signed-off-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
>  drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c | 165 ++++++++++---------
> --
>  drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c | 126 ++++++++--------
>  drivers/phy/mediatek/phy-mtk-hdmi.c        |  51 ++-----
>  drivers/phy/mediatek/phy-mtk-hdmi.h        |   9 +-
>  4 files changed, 158 insertions(+), 193 deletions(-)
> 
> diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
> b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
> index b74c65a1762c..09e0dd7499d8 100644
> --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
> +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
> @@ -69,19 +69,19 @@ static int mtk_hdmi_pll_prepare(struct clk_hw
> *hw)
>  {
>  	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
>  
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6,
> RG_HTPLL_POSDIV_MASK);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON7,
> RG_HTPLL_AUTOK_EN);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6,
> RG_HTPLL_RLH_EN);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON6,
> RG_HTPLL_POSDIV_MASK);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON2,
> RG_HDMITX_EN_MBIAS);
>  	usleep_range(80, 100);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2,
> RG_HDMITX_EN_TX_CKLDO);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_EN_SLDO_MASK);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_EN);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON2,
> RG_HDMITX_EN_TX_CKLDO);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_EN_SLDO_MASK);
>  	usleep_range(80, 100);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2,
> RG_HDMITX_MBIAS_LPF_EN);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_EN_SER_MASK);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_EN_PRED_MASK);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_EN_DRV_MASK);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON2,
> RG_HDMITX_MBIAS_LPF_EN);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_EN_SER_MASK);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_EN_PRED_MASK);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_EN_DRV_MASK);
>  	usleep_range(80, 100);
>  	return 0;
>  }
> @@ -90,19 +90,19 @@ static void mtk_hdmi_pll_unprepare(struct clk_hw
> *hw)
>  {
>  	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
>  
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_EN_DRV_MASK);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_EN_PRED_MASK);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_EN_SER_MASK);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2,
> RG_HDMITX_MBIAS_LPF_EN);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_EN_DRV_MASK);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_EN_PRED_MASK);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_EN_SER_MASK);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON2,
> RG_HDMITX_MBIAS_LPF_EN);
>  	usleep_range(80, 100);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_EN_SLDO_MASK);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2,
> RG_HDMITX_EN_TX_CKLDO);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_EN_SLDO_MASK);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON2,
> RG_HDMITX_EN_TX_CKLDO);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_EN);
>  	usleep_range(80, 100);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2,
> RG_HDMITX_EN_MBIAS);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6,
> RG_HTPLL_POSDIV_MASK);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7,
> RG_HTPLL_AUTOK_EN);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON2,
> RG_HDMITX_EN_MBIAS);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6,
> RG_HTPLL_POSDIV_MASK);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6,
> RG_HTPLL_RLH_EN);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON7,
> RG_HTPLL_AUTOK_EN);
>  	usleep_range(80, 100);
>  }
>  
> @@ -125,37 +125,34 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw
> *hw, unsigned long rate,
>  	else
>  		pos_div = 1;
>  
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6,
> RG_HTPLL_PREDIV_MASK);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6,
> RG_HTPLL_POSDIV_MASK);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2,
> RG_HDMITX_EN_TX_POSDIV);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),
> -			  RG_HTPLL_IC_MASK);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
> -			  RG_HTPLL_IR_MASK);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, (pos_div <<
> RG_HDMITX_TX_POSDIV),
> -			  RG_HDMITX_TX_POSDIV_MASK);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL),
> -			  RG_HTPLL_FBKSEL_MASK);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV),
> -			  RG_HTPLL_FBKDIV_MASK);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN),
> -			  RG_HTPLL_DIVEN_MASK);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP),
> -			  RG_HTPLL_BP_MASK);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC),
> -			  RG_HTPLL_BC_MASK);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR),
> -			  RG_HTPLL_BR_MASK);
> -
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1,
> RG_HDMITX_PRED_IMP);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x3 <<
> RG_HDMITX_PRED_IBIAS),
> -			  RG_HDMITX_PRED_IBIAS_MASK);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_EN_IMP_MASK);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x28 <<
> RG_HDMITX_DRV_IMP),
> -			  RG_HDMITX_DRV_IMP_MASK);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28,
> RG_HDMITX_RESERVE_MASK);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, (0xa <<
> RG_HDMITX_DRV_IBIAS),
> -			  RG_HDMITX_DRV_IBIAS_MASK);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON6,
> RG_HTPLL_PREDIV_MASK);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON6,
> RG_HTPLL_POSDIV_MASK);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON2,
> RG_HDMITX_EN_TX_POSDIV);
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON6,
> RG_HTPLL_IC_MASK, BIT(RG_HTPLL_IC));
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON6,
> RG_HTPLL_IR_MASK, BIT(RG_HTPLL_IR));
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON2,
> RG_HDMITX_TX_POSDIV_MASK,
> +			   (pos_div << RG_HDMITX_TX_POSDIV));
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON6,
> RG_HTPLL_FBKSEL_MASK,
> +			   (1 << RG_HTPLL_FBKSEL));
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON6,
> RG_HTPLL_FBKDIV_MASK,
> +			   (19 << RG_HTPLL_FBKDIV));
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON7,
> RG_HTPLL_DIVEN_MASK,
> +			   (0x2 << RG_HTPLL_DIVEN));
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON6,
> RG_HTPLL_BP_MASK,
> +			   (0xc << RG_HTPLL_BP));
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON6,
> RG_HTPLL_BC_MASK,
> +			   (0x2 << RG_HTPLL_BC));
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON6,
> RG_HTPLL_BR_MASK, BIT(RG_HTPLL_BR));
> +
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON1,
> RG_HDMITX_PRED_IMP);
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON1,
> RG_HDMITX_PRED_IBIAS_MASK,
> +			   (0x3 << RG_HDMITX_PRED_IBIAS));
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_EN_IMP_MASK);
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON1,
> RG_HDMITX_DRV_IMP_MASK,
> +			   (0x28 << RG_HDMITX_DRV_IMP));
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON4,
> RG_HDMITX_RESERVE_MASK, 0x28);
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_DRV_IBIAS_MASK,
> +			   (0xa << RG_HDMITX_DRV_IBIAS));
>  	return 0;
>  }
>  
> @@ -163,10 +160,11 @@ static unsigned long
> mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
>  					      unsigned long
> parent_rate)
>  {
>  	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
> -	unsigned long out_rate, val;
> +	unsigned long out_rate;
> +	u32 val;
>  
> -	val = (readl(hdmi_phy->regs + HDMI_CON6)
> -	       & RG_HTPLL_PREDIV_MASK) >> RG_HTPLL_PREDIV;
> +	regmap_read(hdmi_phy->regmap, HDMI_CON6, &val);
> +	val = (val & RG_HTPLL_PREDIV_MASK) >> RG_HTPLL_PREDIV;
>  	switch (val) {
>  	case 0x00:
>  		out_rate = parent_rate;
> @@ -179,14 +177,15 @@ static unsigned long
> mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
>  		break;
>  	}
>  
> -	val = (readl(hdmi_phy->regs + HDMI_CON6)
> -	       & RG_HTPLL_FBKDIV_MASK) >> RG_HTPLL_FBKDIV;
> +	regmap_read(hdmi_phy->regmap, HDMI_CON6, &val);
> +	val = (val & RG_HTPLL_FBKDIV_MASK) >> RG_HTPLL_FBKDIV;
>  	out_rate *= (val + 1) * 2;
> -	val = (readl(hdmi_phy->regs + HDMI_CON2)
> -	       & RG_HDMITX_TX_POSDIV_MASK);
> +	regmap_read(hdmi_phy->regmap, HDMI_CON2, &val);
> +	val &= RG_HDMITX_TX_POSDIV_MASK;
>  	out_rate >>= (val >> RG_HDMITX_TX_POSDIV);
>  
> -	if (readl(hdmi_phy->regs + HDMI_CON2) & RG_HDMITX_EN_TX_POSDIV)
> +	regmap_read(hdmi_phy->regmap, HDMI_CON2, &val);
> +	if (val & RG_HDMITX_EN_TX_POSDIV)
>  		out_rate /= 5;
>  
>  	return out_rate;
> @@ -202,37 +201,37 @@ static const struct clk_ops
> mtk_hdmi_phy_pll_ops = {
>  
>  static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
>  {
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6,
> RG_HTPLL_POSDIV_MASK);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON7,
> RG_HTPLL_AUTOK_EN);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6,
> RG_HTPLL_RLH_EN);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON6,
> RG_HTPLL_POSDIV_MASK);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON2,
> RG_HDMITX_EN_MBIAS);
>  	usleep_range(80, 100);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2,
> RG_HDMITX_EN_TX_CKLDO);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_EN_SLDO_MASK);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_EN);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON2,
> RG_HDMITX_EN_TX_CKLDO);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_EN_SLDO_MASK);
>  	usleep_range(80, 100);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2,
> RG_HDMITX_MBIAS_LPF_EN);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_EN_SER_MASK);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_EN_PRED_MASK);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_EN_DRV_MASK);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON2,
> RG_HDMITX_MBIAS_LPF_EN);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_EN_SER_MASK);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_EN_PRED_MASK);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_EN_DRV_MASK);
>  	usleep_range(80, 100);
>  }
>  
>  static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
>  {
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_EN_DRV_MASK);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_EN_PRED_MASK);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_EN_SER_MASK);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2,
> RG_HDMITX_MBIAS_LPF_EN);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_EN_DRV_MASK);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_EN_PRED_MASK);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_EN_SER_MASK);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON2,
> RG_HDMITX_MBIAS_LPF_EN);
>  	usleep_range(80, 100);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_EN_SLDO_MASK);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2,
> RG_HDMITX_EN_TX_CKLDO);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_EN_SLDO_MASK);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON2,
> RG_HDMITX_EN_TX_CKLDO);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_EN);
>  	usleep_range(80, 100);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2,
> RG_HDMITX_EN_MBIAS);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6,
> RG_HTPLL_POSDIV_MASK);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7,
> RG_HTPLL_AUTOK_EN);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON2,
> RG_HDMITX_EN_MBIAS);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6,
> RG_HTPLL_POSDIV_MASK);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6,
> RG_HTPLL_RLH_EN);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON7,
> RG_HTPLL_AUTOK_EN);
>  	usleep_range(80, 100);
>  }
>  
> diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
> b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
> index 6cdfdf5a698a..e317bf4a9db9 100644
> --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
> +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
> @@ -111,15 +111,15 @@ static int mtk_hdmi_pll_prepare(struct clk_hw
> *hw)
>  {
>  	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
>  
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1,
> RG_HDMITX_PLL_AUTOK_EN);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_PLL_POSDIV);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
> RG_HDMITX_MHLCK_EN);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1,
> RG_HDMITX_PLL_BIAS_EN);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON1,
> RG_HDMITX_PLL_AUTOK_EN);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_PLL_POSDIV);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON3,
> RG_HDMITX_MHLCK_EN);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON1,
> RG_HDMITX_PLL_BIAS_EN);
>  	usleep_range(100, 150);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_PLL_EN);
>  	usleep_range(100, 150);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1,
> RG_HDMITX_PLL_BIAS_LPF_EN);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1,
> RG_HDMITX_PLL_TXDIV_EN);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON1,
> RG_HDMITX_PLL_BIAS_LPF_EN);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON1,
> RG_HDMITX_PLL_TXDIV_EN);
>  
>  	return 0;
>  }
> @@ -128,14 +128,14 @@ static void mtk_hdmi_pll_unprepare(struct
> clk_hw *hw)
>  {
>  	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
>  
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1,
> RG_HDMITX_PLL_TXDIV_EN);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1,
> RG_HDMITX_PLL_BIAS_LPF_EN);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON1,
> RG_HDMITX_PLL_TXDIV_EN);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON1,
> RG_HDMITX_PLL_BIAS_LPF_EN);
>  	usleep_range(100, 150);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_PLL_EN);
>  	usleep_range(100, 150);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1,
> RG_HDMITX_PLL_BIAS_EN);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_PLL_POSDIV);
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1,
> RG_HDMITX_PLL_AUTOK_EN);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON1,
> RG_HDMITX_PLL_BIAS_EN);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_PLL_POSDIV);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON1,
> RG_HDMITX_PLL_AUTOK_EN);
>  	usleep_range(100, 150);
>  }
>  
> @@ -177,65 +177,59 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw
> *hw, unsigned long rate,
>  		div = 1;
>  	}
>  
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
> -			  (pre_div << PREDIV_SHIFT),
> RG_HDMITX_PLL_PREDIV);
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0,
> RG_HDMITX_PLL_POSDIV);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
> -			  (0x1 << PLL_IC_SHIFT) | (0x1 <<
> PLL_IR_SHIFT),
> -			  RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
> -			  (div << PLL_TXDIV_SHIFT),
> RG_HDMITX_PLL_TXDIV);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
> -			  (0x1 << PLL_FBKSEL_SHIFT) | (19 <<
> PLL_FBKDIV_SHIFT),
> -			  RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
> -			  (0x2 << PLL_DIVEN_SHIFT),
> RG_HDMITX_PLL_DIVEN);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
> -			  (0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT)
> |
> -			  (0x1 << PLL_BR_SHIFT),
> -			  RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
> -			  RG_HDMITX_PLL_BR);
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_PLL_PREDIV,
> +			   (pre_div << PREDIV_SHIFT));
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON0,
> RG_HDMITX_PLL_POSDIV);
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON0,
> +			   RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR,
> +			   BIT(PLL_IC_SHIFT) | BIT(PLL_IR_SHIFT));
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON1,
> RG_HDMITX_PLL_TXDIV,
> +			   (div << PLL_TXDIV_SHIFT));
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON0,
> +			   RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV,
> +			  BIT(PLL_FBKSEL_SHIFT) | (19 <<
> PLL_FBKDIV_SHIFT));
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON1,
> RG_HDMITX_PLL_DIVEN,
> +			   (0x2 << PLL_DIVEN_SHIFT));
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON0,
> +			   RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
> RG_HDMITX_PLL_BR,
> +			   (0xc << PLL_BP_SHIFT) | (0x2 <<
> PLL_BC_SHIFT) |
> +			   (0x1 << PLL_BR_SHIFT));
>  	if (rate < 165000000) {
> -		mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
> +		regmap_clear_bits(hdmi_phy->regmap, HDMI_CON3,
>  					RG_HDMITX_PRD_IMP_EN);
>  		pre_ibias = 0x3;
>  		imp_en = 0x0;
>  		hdmi_ibias = hdmi_phy->ibias;
>  	} else {
> -		mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
> +		regmap_set_bits(hdmi_phy->regmap, HDMI_CON3,
>  				      RG_HDMITX_PRD_IMP_EN);
>  		pre_ibias = 0x6;
>  		imp_en = 0xf;
>  		hdmi_ibias = hdmi_phy->ibias_up;
>  	}
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
> -			  (pre_ibias << PRD_IBIAS_CLK_SHIFT) |
> -			  (pre_ibias << PRD_IBIAS_D2_SHIFT) |
> -			  (pre_ibias << PRD_IBIAS_D1_SHIFT) |
> -			  (pre_ibias << PRD_IBIAS_D0_SHIFT),
> -			  RG_HDMITX_PRD_IBIAS_CLK |
> -			  RG_HDMITX_PRD_IBIAS_D2 |
> -			  RG_HDMITX_PRD_IBIAS_D1 |
> -			  RG_HDMITX_PRD_IBIAS_D0);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
> -			  (imp_en << DRV_IMP_EN_SHIFT),
> -			  RG_HDMITX_DRV_IMP_EN);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
> -			  (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT)
> |
> -			  (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
> -			  (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
> -			  (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
> -			  RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2
> |
> -			  RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
> -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
> -			  (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) |
> -			  (hdmi_ibias << DRV_IBIAS_D2_SHIFT) |
> -			  (hdmi_ibias << DRV_IBIAS_D1_SHIFT) |
> -			  (hdmi_ibias << DRV_IBIAS_D0_SHIFT),
> -			  RG_HDMITX_DRV_IBIAS_CLK |
> -			  RG_HDMITX_DRV_IBIAS_D2 |
> -			  RG_HDMITX_DRV_IBIAS_D1 |
> -			  RG_HDMITX_DRV_IBIAS_D0);
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON4,
> +			   RG_HDMITX_PRD_IBIAS_CLK |
> RG_HDMITX_PRD_IBIAS_D2 |
> +			   RG_HDMITX_PRD_IBIAS_D1 |
> RG_HDMITX_PRD_IBIAS_D0,
> +			   (pre_ibias << PRD_IBIAS_CLK_SHIFT) |
> +			   (pre_ibias << PRD_IBIAS_D2_SHIFT) |
> +			   (pre_ibias << PRD_IBIAS_D1_SHIFT) |
> +			   (pre_ibias << PRD_IBIAS_D0_SHIFT));
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON3,
> RG_HDMITX_DRV_IMP_EN,
> +			   (imp_en << DRV_IMP_EN_SHIFT));
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON6,
> +			   RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2
> |
> +			   RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0,
> +			   (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT)
> |
> +			   (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
> +			   (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
> +			   (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT));
> +	regmap_update_bits(hdmi_phy->regmap, HDMI_CON5,
> +			   RG_HDMITX_DRV_IBIAS_CLK |
> RG_HDMITX_DRV_IBIAS_D2 |
> +			   RG_HDMITX_DRV_IBIAS_D1 |
> RG_HDMITX_DRV_IBIAS_D0,
> +			   (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) |
> +			   (hdmi_ibias << DRV_IBIAS_D2_SHIFT) |
> +			   (hdmi_ibias << DRV_IBIAS_D1_SHIFT) |
> +			   (hdmi_ibias << DRV_IBIAS_D0_SHIFT));
>  	return 0;
>  }
>  
> @@ -257,17 +251,15 @@ static const struct clk_ops
> mtk_hdmi_phy_pll_ops = {
>  
>  static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
>  {
> -	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
> -			      RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN |
> -			      RG_HDMITX_DRV_EN);
> +	regmap_set_bits(hdmi_phy->regmap, HDMI_CON3,
> +			RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN |
> RG_HDMITX_DRV_EN);
>  	usleep_range(100, 150);
>  }
>  
>  static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
>  {
> -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
> -				RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN |
> -				RG_HDMITX_SER_EN);
> +	regmap_clear_bits(hdmi_phy->regmap, HDMI_CON3,
> +			  RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN |
> RG_HDMITX_SER_EN);
>  }
>  
>  struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
> diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c
> b/drivers/phy/mediatek/phy-mtk-hdmi.c
> index 5fb4217fb8e0..707e90691e6e 100644
> --- a/drivers/phy/mediatek/phy-mtk-hdmi.c
> +++ b/drivers/phy/mediatek/phy-mtk-hdmi.c
> @@ -15,39 +15,6 @@ static const struct phy_ops mtk_hdmi_phy_dev_ops =
> {
>  	.owner = THIS_MODULE,
>  };
>  
> -void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32
> offset,
> -			     u32 bits)
> -{
> -	void __iomem *reg = hdmi_phy->regs + offset;
> -	u32 tmp;
> -
> -	tmp = readl(reg);
> -	tmp &= ~bits;
> -	writel(tmp, reg);
> -}
> -
> -void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32
> offset,
> -			   u32 bits)
> -{
> -	void __iomem *reg = hdmi_phy->regs + offset;
> -	u32 tmp;
> -
> -	tmp = readl(reg);
> -	tmp |= bits;
> -	writel(tmp, reg);
> -}
> -
> -void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
> -		       u32 val, u32 mask)
> -{
> -	void __iomem *reg = hdmi_phy->regs + offset;
> -	u32 tmp;
> -
> -	tmp = readl(reg);
> -	tmp = (tmp & ~mask) | (val & mask);
> -	writel(tmp, reg);
> -}
> -
>  inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
>  {
>  	return container_of(hw, struct mtk_hdmi_phy, pll_hw);
> @@ -96,6 +63,13 @@ static void mtk_hdmi_phy_clk_get_data(struct
> mtk_hdmi_phy *hdmi_phy,
>  	clk_init->ops = hdmi_phy->conf->hdmi_phy_clk_ops;
>  }
>  
> +static const struct regmap_config mtk_hdmi_phy_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.disable_locking = true,
> +};
> +
>  static int mtk_hdmi_phy_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
> @@ -109,15 +83,20 @@ static int mtk_hdmi_phy_probe(struct
> platform_device *pdev)
>  
>  	struct phy *phy;
>  	struct phy_provider *phy_provider;
> +	void __iomem *regs;
>  	int ret;
>  
>  	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
>  	if (!hdmi_phy)
>  		return -ENOMEM;
>  
> -	hdmi_phy->regs = devm_platform_ioremap_resource(pdev, 0);
> -	if (IS_ERR(hdmi_phy->regs))
> -		return PTR_ERR(hdmi_phy->regs);
> +	regs = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(regs))
> +		return PTR_ERR(regs);
> +
> +	hdmi_phy->regmap = devm_regmap_init_mmio(dev, regs,
> &mtk_hdmi_phy_regmap_config);
> +	if (IS_ERR(hdmi_phy->regmap))
> +		return PTR_ERR(hdmi_phy->regmap);
>  
>  	ref_clk = devm_clk_get(dev, "pll_ref");
>  	if (IS_ERR(ref_clk)) {
> diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.h
> b/drivers/phy/mediatek/phy-mtk-hdmi.h
> index dcf9bb13699b..a0571271d730 100644
> --- a/drivers/phy/mediatek/phy-mtk-hdmi.h
> +++ b/drivers/phy/mediatek/phy-mtk-hdmi.h
> @@ -15,6 +15,7 @@
>  #include <linux/of_device.h>
>  #include <linux/phy/phy.h>
>  #include <linux/platform_device.h>
> +#include <linux/regmap.h>
>  #include <linux/types.h>
>  
>  struct mtk_hdmi_phy;
> @@ -28,7 +29,7 @@ struct mtk_hdmi_phy_conf {
>  };
>  
>  struct mtk_hdmi_phy {
> -	void __iomem *regs;
> +	struct regmap *regmap;
>  	struct device *dev;
>  	struct mtk_hdmi_phy_conf *conf;
>  	struct clk *pll;
> @@ -42,12 +43,6 @@ struct mtk_hdmi_phy {
>  	unsigned int ibias_up;
>  };
>  
> -void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32
> offset,
> -			     u32 bits);
> -void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32
> offset,
> -			   u32 bits);
> -void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
> -		       u32 val, u32 mask);
>  struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
>  
>  extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;