Re: [PATCH] net: macb: Set MDIO clock divisor for pclk higher than 160MHz

[Nicolas Ferre <nicolas.ferre@microchip.com>]

Andrew,

On 16/03/2023 at 20:34, Andrew Lunn wrote:
> On Thu, Mar 16, 2023 at 10:03:39AM +0000, Bartosz Wawrzyniak wrote:
>> Currently macb sets clock divisor for pclk up to 160 MHz.
>> Function gem_mdc_clk_div was updated to enable divisor
>> for higher values of pclk.
>>
>> Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
>> ---
>>   drivers/net/ethernet/cadence/macb.h      | 2 ++
>>   drivers/net/ethernet/cadence/macb_main.c | 6 +++++-
>>   2 files changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
>> index 14dfec4db8f9..c1fc91c97cee 100644
>> --- a/drivers/net/ethernet/cadence/macb.h
>> +++ b/drivers/net/ethernet/cadence/macb.h
>> @@ -692,6 +692,8 @@
>>   #define GEM_CLK_DIV48                                3
>>   #define GEM_CLK_DIV64                                4
>>   #define GEM_CLK_DIV96                                5
>> +#define GEM_CLK_DIV128                               6
>> +#define GEM_CLK_DIV224                               7
> 
> Do these divisors exist for all variants? I'm just wondering why these
> are being added now, rather than back in 2011-03-09.

I see them existing in all variants of "GEM" controller and the older 
"MACB" uses a different path so I think that we are save enabling these 
values.

The values were not added back in the days because the SoC where the 
controller was used didn't reach the frequencies that we are observing 
today for pclk. Divisors weren't needed and field even not completely 
described in Microchip datasheets.

Hope that this sheds some light. Best regards,
   Nicolas

-- 
Nicolas Ferre