Re: [PATCH v9 04/10] ASoC: qcom: Add QAIF CPU DAI ops, regmap, DT parsing and platform init

[Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>]

On 10/13/26 6:51 AM, Harendra Gautam wrote:
> Add the QAIF CPU DAI driver to support Qualcomm audio interface paths
> used for CDC DMA and serial AIF audio links.
> 
> Implement CIF DAI operations for CDC DMA paths, including channel mask
> programming and dynamic clock control. Implement AIF DAI operations for
> MI2S, TDM and PCM paths, including format setup, slot and lane
> configuration, bit clock management and stream enable handling.
> 
> Also add the QAIF MMIO regmap setup, parse per-interface configuration
> from devicetree, manage required clocks and register the CPU DAI
> component.
> 
> Signed-off-by: Harendra Gautam <harendra.gautam@oss.qualcomm.com>
> ---
>  sound/soc/qcom/qaif-cpu.c | 886 ++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 886 insertions(+)
> 
> +	}
> +
> +	idx = v->get_dma_idx(dai_id);
> +	if (idx < 0) {
> +		dev_err(rtd->dev, "Invalid DMA index: %d\n", idx);
> +		return -EINVAL;
> +	}


This is repeated like so many times in this file,
may be consider a helper,
> +
> +	reg = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
> +		QAIF_CDC_RDDMA_INTF_CFG_REG(v, idx) :
> +		QAIF_CDC_WRDMA_INTF_CFG_REG(v, idx);
> +
> +	return regmap_update_bits(drvdata->audio_qaif_map, reg,
> +				  QAIF_CIF_INTF_ACTIVE_CH_MASK,
> +				  regval << QAIF_CIF_INTF_ACTIVE_CH_SHIFT);
> +}
> +> +
> +static const struct regmap_config audio_qaif_regmap_config = {
> +	.name		= "audio_qaif_cpu",
> +	.reg_bits	= 32,
> +	.reg_stride	= 4,
> +	.val_bits	= 32,
> +	.cache_type	= REGCACHE_NONE,


> +};
> +
> +static int of_qaif_parse_aif_intf_cfg(struct device *dev,
> +				      struct qaif_drv_data *data)
> +{
> +	const struct qaif_variant *v = data->variant;
> +	struct device_node *np = dev->of_node;
> +	struct device_node *intf_np;
> +	struct qaif_aif_config *cfg;
> +	int ret;
> +	u32 dai_id;
> +	int intf_idx;
> +	int num_interfaces = 0;
> +	u32 val_buf[QAIF_MAX_LANES];
> +	int j, n;
> +	unsigned long configured_intf_mask = 0;
> +
> +	for_each_child_of_node(np, intf_np) {
> +		if (!of_property_present(intf_np, "reg"))

Do you have anyother childs that will not have reg?

> +			continue;
> +
> +		if (num_interfaces >= QAIF_MAX_AIF_CFG_CNT) {

This limit should be part of dt-bindings, is this hardware limitation or
software?


> +			dev_warn(dev, "Too many AIF interfaces, limiting to %d\n",
> +				 QAIF_MAX_AIF_CFG_CNT);
> +			of_node_put(intf_np);
use scoped ones here.
> +			break;
> +		}
> +
> +		ret = of_property_read_u32(intf_np, "reg", &dai_id);
> +		if (ret) {
> +			dev_err(dev, "Missing reg for interface %pOFn\n", intf_np);
> +			of_node_put(intf_np);
> +			return ret;
> +		}
> +
> +		intf_idx = v->get_dma_idx(dai_id);
> +		if (intf_idx < 0) {
> +			dev_err(dev, "Invalid DAI ID %d for interface %pOFn\n",
> +				dai_id, intf_np);
> +			of_node_put(intf_np);
> +			return -EINVAL;
> +		}
> +		if (intf_idx >= ARRAY_SIZE(data->aif_intf_cfg)) {
> +			dev_err(dev, "DAI ID %d maps to out-of-range intf_idx %d\n",
> +				dai_id, intf_idx);
> +			of_node_put(intf_np);
> +			return -EINVAL;
> +		}
> +
> +		if (configured_intf_mask & BIT(intf_idx)) {
> +			dev_err(dev, "Duplicate reg %d for interface %pOFn\n",
> +				dai_id, intf_np);
> +			of_node_put(intf_np);
> +			return -EINVAL;
> +		}
> +		configured_intf_mask |= BIT(intf_idx);
> +
> +		cfg = &data->aif_intf_cfg[intf_idx];
> +		if (v->aif_full_cycle_en)
> +			cfg->full_cycle_en = v->aif_full_cycle_en[intf_idx];
> +		if (v->aif_ctrl_data_oe)
> +			cfg->ctrl_data_oe = v->aif_ctrl_data_oe[intf_idx];
> +		if (v->aif_loopback_en)
> +			cfg->loopback_en = v->aif_loopback_en[intf_idx];
> +
> +		switch (snd_soc_daifmt_parse_format(intf_np, NULL) &
> +			SND_SOC_DAIFMT_FORMAT_MASK) {
> +		case SND_SOC_DAIFMT_I2S:
> +			cfg->sync_mode = QAIF_AIF_SYNC_MODE_LONG;
> +			cfg->sync_delay = QAIF_AIF_SYNC_DELAY_ONE;
> +			cfg->invert_sync = true;
> +			break;
> +		case SND_SOC_DAIFMT_DSP_A:
> +			cfg->sync_mode = QAIF_AIF_SYNC_MODE_ONE_SLOT;
> +			cfg->sync_delay = QAIF_AIF_SYNC_DELAY_ONE;
> +			break;
> +		case SND_SOC_DAIFMT_DSP_B:
> +			cfg->sync_mode = QAIF_AIF_SYNC_MODE_SHORT;
> +			cfg->sync_delay = QAIF_AIF_SYNC_DELAY_SAME;
> +			break;
> +		default:
> +			break;

Error?


> +		}
> +
> +		if (!qaif_is_aif_mi2s_port(dai_id)) {
> +			ret = of_property_read_u32(intf_np, "dai-tdm-slot-width",
> +						   &cfg->slot_width);
> +			if (ret || !cfg->slot_width) {
> +				dev_err(dev, "Missing/invalid dai-tdm-slot-width for %pOFn\n",
> +					intf_np);
> +				of_node_put(intf_np);
> +				return ret ? ret : -EINVAL;
> +			}
> +			ret = of_property_read_u32(intf_np, "dai-tdm-slot-num",
> +						   &cfg->slot_num);
> +			if (ret || !cfg->slot_num) {
> +				dev_err(dev, "Missing/invalid dai-tdm-slot-num for %pOFn\n",
> +					intf_np);
> +				of_node_put(intf_np);
> +				return ret ? ret : -EINVAL;
> +			}
> +			snd_soc_of_get_slot_mask(intf_np, "dai-tdm-slot-rx-mask",
> +						 &cfg->slot_en_rx_mask);
> +			snd_soc_of_get_slot_mask(intf_np, "dai-tdm-slot-tx-mask",
> +						 &cfg->slot_en_tx_mask);
> +			if (!cfg->slot_en_rx_mask && !cfg->slot_en_tx_mask) {
> +				dev_err(dev, "No active TDM slots for %pOFn\n",
> +					intf_np);
> +				of_node_put(intf_np);
> +				return -EINVAL;
> +			}
> +		}
> +
> +		n = of_property_read_variable_u32_array(intf_np,
> +							"qcom,qaif-aif-lane-map",
> +							val_buf, 1, QAIF_MAX_LANES);
> +		if (n < 0) {
> +			dev_err(dev, "Missing qcom,qaif-aif-lane-map for %pOFn\n",
> +				intf_np);
> +			of_node_put(intf_np);
> +			return n;
> +		}
> +		for (j = 0; j < n; j++) {
> +			if (val_buf[j] > 1) {
> +				dev_err(dev, "Invalid lane-map value %u for %pOFn\n",
> +					val_buf[j], intf_np);
> +				of_node_put(intf_np);
> +				return -EINVAL;
> +			}
> +			cfg->lane_en_mask |= BIT(j);
> +			if (val_buf[j])
> +				cfg->lane_dir_mask |= BIT(j);
> +		}
> +
> +		num_interfaces++;
> +	}
> +
> +	return 0;
> +}
> +
> +/**
> + * asoc_qcom_qaif_cpu_platform_probe - Probe the QAIF CPU and platform driver
> + * @pdev: Platform device
> + *
> + * Initialises the QAIF regmap, parses DT, sets up clocks and registers
> + * the CPU DAI component and PCM platform.
> + *
> + * Return: 0 on success, negative error code on failure.
> + */
> +int asoc_qcom_qaif_cpu_platform_probe(struct platform_device *pdev)
> +{
> +	struct regmap_config regmap_cfg = audio_qaif_regmap_config;
> +	struct qaif_drv_data *drvdata;
> +	struct resource *res;
> +	const struct qaif_variant *variant;
> +	struct device *dev = &pdev->dev;
> +	const struct of_device_id *match;
> +	int ret, i, dai_id, idx;
> +
> +	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> +	if (!drvdata)
> +		return dev_err_probe(dev, -ENOMEM, "Failed to allocate driver data\n");
> +	platform_set_drvdata(pdev, drvdata);
> +
> +	match = of_match_device(dev->driver->of_match_table, dev);
> +	if (!match || !match->data)
> +		return dev_err_probe(dev, -EINVAL, "No matching device data\n");
> +
> +	drvdata->variant = match->data;
> +	variant = drvdata->variant;

plese use device_get_match_data() here,


> +
> +	if (!variant->get_dma_idx)
> +		return dev_err_probe(dev, -EINVAL,
> +				     "variant is missing get_dma_idx callback\n");
> +
> +	ret = of_qaif_parse_aif_intf_cfg(dev, drvdata);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "Failed to parse aif interfaces\n");
> +
> +	drvdata->audio_qaif = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(drvdata->audio_qaif))
> +		return dev_err_probe(dev, PTR_ERR(drvdata->audio_qaif),
> +				     "Failed to ioremap QAIF registers\n");
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res)
> +		return dev_err_probe(dev, -EINVAL, "Failed to get MMIO resource\n");
> +
> +	regmap_cfg.max_register = resource_size(res) - regmap_cfg.reg_stride;
> +	drvdata->audio_qaif_map = devm_regmap_init_mmio(dev, drvdata->audio_qaif,
> +							&regmap_cfg);
> +	if (IS_ERR(drvdata->audio_qaif_map))
> +		return dev_err_probe(dev, PTR_ERR(drvdata->audio_qaif_map),
> +				     "Failed to init regmap\n");
> +
> +	drvdata->aud_dma_clk = devm_clk_get(dev, "aud_dma");
> +	if (IS_ERR(drvdata->aud_dma_clk))
> +		return dev_err_probe(dev, PTR_ERR(drvdata->aud_dma_clk),
> +				     "Failed to get aud_dma clock\n");
> +
> +	drvdata->aud_dma_mem_clk = devm_clk_get(dev, "aud_dma_mem");
> +	if (IS_ERR(drvdata->aud_dma_mem_clk))
> +		return dev_err_probe(dev, PTR_ERR(drvdata->aud_dma_mem_clk),
> +				     "Failed to get aud_dma_mem clock\n");
> +
> +	for (i = 0; i < variant->num_dai; i++) {
> +		dai_id = variant->dai_driver[i].id;
> +		if (qaif_is_cif_port(dai_id))
> +			continue;
> +		idx = variant->get_dma_idx(dai_id);
> +		if (idx < 0)
> +			continue;
> +
> +		if (drvdata->mi2s_bit_clk[idx])
> +			continue;
> +