From: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com>
To: Harendra Gautam <harendra.gautam@oss.qualcomm.com>,
Srinivas Kandagatla <srini@kernel.org>
Cc: Mark Brown <broonie@kernel.org>,
Liam Girdwood <lgirdwood@gmail.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>,
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>,
linux-sound@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>,
Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>,
Kumar Anurag Singh <kumar.singh@oss.qualcomm.com>,
Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>,
ajay.nandam@oss.qualcomm.com
Subject: Re: [PATCH v9 09/10] ASoC: qcom: Add Shikra QAIF support
Date: Thu, 15 Oct 2026 12:32:17 +0530 [thread overview]
Message-ID: <b0a3b094-80a8-4269-8f3b-ed1e676a6fa2@oss.qualcomm.com> (raw)
In-Reply-To: <20261013-b4-qaif-shikra-audio-v9-9-f3022e28f2fd@oss.qualcomm.com>
On 10/13/2026 11:21 AM, Harendra Gautam wrote:
> Add the Shikra variant data for the Qualcomm Audio Interface driver so
> the common QAIF code can bind to the Shikra QAIF device and expose the
> SoC-specific DAIs.
>
> Provide the Shikra DMA-to-DAI mappings, DMA and SHRAM layout, clock
> names, DAI driver data and power-management hooks required by the QAIF
> driver. Add the Kconfig symbol and Makefile entries needed to build the
> new variant.
>
> Signed-off-by: Harendra Gautam <harendra.gautam@oss.qualcomm.com>
LGTM
Reviewed-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com>
> ---
> sound/soc/qcom/Kconfig | 10 +
> sound/soc/qcom/Makefile | 3 +
> sound/soc/qcom/qaif-shikra.c | 445 +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 458 insertions(+)
>
> diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig
> index e6e24f3b9922..b7088b1e5cad 100644
> --- a/sound/soc/qcom/Kconfig
> +++ b/sound/soc/qcom/Kconfig
> @@ -71,6 +71,16 @@ config SND_SOC_QCOM_COMMON
> config SND_SOC_QCOM_SDW
> tristate
>
> +config SND_SOC_QCOM_QAIF
> + tristate "Qualcomm QAIF audio interface support"
> + depends on COMMON_CLK
> + select REGMAP_MMIO
> + help
> + Say Y or M to enable the Qualcomm Audio Interface (QAIF) driver
> + for the Shikra audio platform. QAIF is a DMA-based audio
> + subsystem that moves PCM data between memory and external serial
> + audio interfaces (AIF) and internal codec interfaces (CIF).
> +
> config SND_SOC_QDSP6_COMMON
> tristate
>
> diff --git a/sound/soc/qcom/Makefile b/sound/soc/qcom/Makefile
> index 985ce2ae286b..cf50b7a24bcf 100644
> --- a/sound/soc/qcom/Makefile
> +++ b/sound/soc/qcom/Makefile
> @@ -47,3 +47,6 @@ obj-$(CONFIG_SND_SOC_QCOM_OFFLOAD_UTILS) += snd-soc-qcom-offload-utils.o
>
> #DSP lib
> obj-$(CONFIG_SND_SOC_QDSP6) += qdsp6/
> +
> +snd-soc-qcom-qaif-y := qaif-cpu.o qaif-platform.o qaif-shikra.o
> +obj-$(CONFIG_SND_SOC_QCOM_QAIF) += snd-soc-qcom-qaif.o
> diff --git a/sound/soc/qcom/qaif-shikra.c b/sound/soc/qcom/qaif-shikra.c
> new file mode 100644
> index 000000000000..2db3995a2de0
> --- /dev/null
> +++ b/sound/soc/qcom/qaif-shikra.c
> @@ -0,0 +1,445 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + *
> + * qaif-shikra.c -- ALSA SoC CPU-Platform DAI driver for QTi QAIF
> + */
> +
> +#include <linux/module.h>
> +#include <linux/pm.h>
> +#include <sound/pcm.h>
> +#include <sound/soc.h>
> +#include "qaif.h"
> +
> +static const struct qaif_dmaidx_dai_map shikra_mi2s_dma_dai_map[] = {
> + { AIF_MI2S_RX_0, QAIF_DMA_IDX0 },
> + { AIF_MI2S_RX_1, QAIF_DMA_IDX1 },
> + { AIF_MI2S_RX_2, QAIF_DMA_IDX2 },
> + { AIF_MI2S_RX_3, QAIF_DMA_IDX3 },
> + { AIF_MI2S_TX_0, QAIF_DMA_IDX0 },
> + { AIF_MI2S_TX_1, QAIF_DMA_IDX1 },
> + { AIF_MI2S_TX_2, QAIF_DMA_IDX2 },
> + { AIF_MI2S_TX_3, QAIF_DMA_IDX3 },
> +};
> +
> +static const struct qaif_dmaidx_dai_map shikra_tdm_dma_dai_map[] = {
> + { AIF_TDM_RX_0, QAIF_DMA_IDX0 },
> + { AIF_TDM_RX_1, QAIF_DMA_IDX1 },
> + { AIF_TDM_RX_2, QAIF_DMA_IDX2 },
> + { AIF_TDM_RX_3, QAIF_DMA_IDX3 },
> + { AIF_TDM_TX_0, QAIF_DMA_IDX0 },
> + { AIF_TDM_TX_1, QAIF_DMA_IDX1 },
> + { AIF_TDM_TX_2, QAIF_DMA_IDX2 },
> + { AIF_TDM_TX_3, QAIF_DMA_IDX3 },
> +};
> +
> +static const struct qaif_dmaidx_dai_map shikra_cif_dma_dai_map[] = {
> + { RX_CODEC_DMA_RX_0, QAIF_DMA_IDX0 },
> + { RX_CODEC_DMA_RX_1, QAIF_DMA_IDX1 },
> + { VA_CODEC_DMA_TX_0, QAIF_DMA_IDX0 },
> + { VA_CODEC_DMA_TX_1, QAIF_DMA_IDX1 },
> +};
> +
> +static struct snd_soc_dai_driver shikra_qaif_cpu_dai_driver[] = {
> + {
> + .id = AIF_MI2S_RX_0,
> + .name = "MI2S AIF RX Zero",
> + .playback = {
> + .stream_name = "MI2S AIF RX Zero Playback",
> + .formats = SNDRV_PCM_FMTBIT_S16 |
> + SNDRV_PCM_FMTBIT_S32,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .channels_min = 1,
> + .channels_max = 2,
> + },
> + .ops = &asoc_qcom_qaif_aif_cpu_dai_ops,
> + }, {
> + .id = AIF_MI2S_TX_0,
> + .name = "MI2S AIF TX Zero",
> + .capture = {
> + .stream_name = "MI2S AIF TX Zero Capture",
> + .formats = SNDRV_PCM_FMTBIT_S16 |
> + SNDRV_PCM_FMTBIT_S32,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .channels_min = 1,
> + .channels_max = 2,
> + },
> + .ops = &asoc_qcom_qaif_aif_cpu_dai_ops,
> + }, {
> + .id = AIF_TDM_RX_0,
> + .name = "TDM AIF RX Zero",
> + .playback = {
> + .stream_name = "TDM AIF RX Zero Playback",
> + .formats = SNDRV_PCM_FMTBIT_S16 |
> + SNDRV_PCM_FMTBIT_S24 |
> + SNDRV_PCM_FMTBIT_S32,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .channels_min = 1,
> + .channels_max = 8,
> + },
> + .ops = &asoc_qcom_qaif_aif_cpu_dai_ops,
> + }, {
> + .id = AIF_TDM_TX_0,
> + .name = "TDM AIF TX Zero",
> + .capture = {
> + .stream_name = "TDM AIF TX Zero Capture",
> + .formats = SNDRV_PCM_FMTBIT_S16 |
> + SNDRV_PCM_FMTBIT_S24 |
> + SNDRV_PCM_FMTBIT_S32,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .channels_min = 1,
> + .channels_max = 8,
> + },
> + .ops = &asoc_qcom_qaif_aif_cpu_dai_ops,
> + }, {
> + .id = AIF_MI2S_RX_1,
> + .name = "MI2S AIF RX One",
> + .playback = {
> + .stream_name = "MI2S AIF RX One Playback",
> + .formats = SNDRV_PCM_FMTBIT_S16 |
> + SNDRV_PCM_FMTBIT_S32,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .channels_min = 1,
> + .channels_max = 2,
> + },
> + .ops = &asoc_qcom_qaif_aif_cpu_dai_ops,
> + }, {
> + .id = AIF_MI2S_TX_1,
> + .name = "MI2S AIF TX One",
> + .capture = {
> + .stream_name = "MI2S AIF TX One Capture",
> + .formats = SNDRV_PCM_FMTBIT_S16 |
> + SNDRV_PCM_FMTBIT_S32,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .channels_min = 1,
> + .channels_max = 2,
> + },
> + .ops = &asoc_qcom_qaif_aif_cpu_dai_ops,
> + }, {
> + .id = AIF_TDM_RX_1,
> + .name = "TDM AIF RX One",
> + .playback = {
> + .stream_name = "TDM AIF RX One Playback",
> + .formats = SNDRV_PCM_FMTBIT_S16 |
> + SNDRV_PCM_FMTBIT_S24 |
> + SNDRV_PCM_FMTBIT_S32,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .channels_min = 1,
> + .channels_max = 8,
> + },
> + .ops = &asoc_qcom_qaif_aif_cpu_dai_ops,
> + }, {
> + .id = AIF_TDM_TX_1,
> + .name = "TDM AIF TX One",
> + .capture = {
> + .stream_name = "TDM AIF TX One Capture",
> + .formats = SNDRV_PCM_FMTBIT_S16 |
> + SNDRV_PCM_FMTBIT_S24 |
> + SNDRV_PCM_FMTBIT_S32,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .channels_min = 1,
> + .channels_max = 8,
> + },
> + .ops = &asoc_qcom_qaif_aif_cpu_dai_ops,
> + }, {
> + .id = AIF_MI2S_RX_2,
> + .name = "MI2S AIF RX Two",
> + .playback = {
> + .stream_name = "MI2S AIF RX Two Playback",
> + .formats = SNDRV_PCM_FMTBIT_S16 |
> + SNDRV_PCM_FMTBIT_S32,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .channels_min = 1,
> + .channels_max = 2,
> + },
> + .ops = &asoc_qcom_qaif_aif_cpu_dai_ops,
> + }, {
> + .id = AIF_MI2S_TX_2,
> + .name = "MI2S AIF TX Two",
> + .capture = {
> + .stream_name = "MI2S AIF TX Two Capture",
> + .formats = SNDRV_PCM_FMTBIT_S16 |
> + SNDRV_PCM_FMTBIT_S32,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .channels_min = 1,
> + .channels_max = 2,
> + },
> + .ops = &asoc_qcom_qaif_aif_cpu_dai_ops,
> + }, {
> + .id = AIF_TDM_RX_2,
> + .name = "TDM AIF RX Two",
> + .playback = {
> + .stream_name = "TDM AIF RX Two Playback",
> + .formats = SNDRV_PCM_FMTBIT_S16 |
> + SNDRV_PCM_FMTBIT_S24 |
> + SNDRV_PCM_FMTBIT_S32,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .channels_min = 1,
> + .channels_max = 8,
> + },
> + .ops = &asoc_qcom_qaif_aif_cpu_dai_ops,
> + }, {
> + .id = AIF_TDM_TX_2,
> + .name = "TDM AIF TX Two",
> + .capture = {
> + .stream_name = "TDM AIF TX Two Capture",
> + .formats = SNDRV_PCM_FMTBIT_S16 |
> + SNDRV_PCM_FMTBIT_S24 |
> + SNDRV_PCM_FMTBIT_S32,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .channels_min = 1,
> + .channels_max = 8,
> + },
> + .ops = &asoc_qcom_qaif_aif_cpu_dai_ops,
> + }, {
> + .id = AIF_MI2S_RX_3,
> + .name = "MI2S AIF RX Three",
> + .playback = {
> + .stream_name = "MI2S AIF RX Three Playback",
> + .formats = SNDRV_PCM_FMTBIT_S16 |
> + SNDRV_PCM_FMTBIT_S32,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .channels_min = 1,
> + .channels_max = 2,
> + },
> + .ops = &asoc_qcom_qaif_aif_cpu_dai_ops,
> + }, {
> + .id = AIF_MI2S_TX_3,
> + .name = "MI2S AIF TX Three",
> + .capture = {
> + .stream_name = "MI2S AIF TX Three Capture",
> + .formats = SNDRV_PCM_FMTBIT_S16 |
> + SNDRV_PCM_FMTBIT_S32,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .channels_min = 1,
> + .channels_max = 2,
> + },
> + .ops = &asoc_qcom_qaif_aif_cpu_dai_ops,
> + }, {
> + .id = AIF_TDM_RX_3,
> + .name = "TDM AIF RX Three",
> + .playback = {
> + .stream_name = "TDM AIF RX Three Playback",
> + .formats = SNDRV_PCM_FMTBIT_S16 |
> + SNDRV_PCM_FMTBIT_S24 |
> + SNDRV_PCM_FMTBIT_S32,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .channels_min = 1,
> + .channels_max = 8,
> + },
> + .ops = &asoc_qcom_qaif_aif_cpu_dai_ops,
> + }, {
> + .id = AIF_TDM_TX_3,
> + .name = "TDM AIF TX Three",
> + .capture = {
> + .stream_name = "TDM AIF TX Three Capture",
> + .formats = SNDRV_PCM_FMTBIT_S16 |
> + SNDRV_PCM_FMTBIT_S24 |
> + SNDRV_PCM_FMTBIT_S32,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .channels_min = 1,
> + .channels_max = 8,
> + },
> + .ops = &asoc_qcom_qaif_aif_cpu_dai_ops,
> + }, {
> + .id = RX_CODEC_DMA_RX_0,
> + .name = "RX CDC DMA RX0",
> + .playback = {
> + .stream_name = "RX CDC DMA RX0 Playback",
> + .formats = SNDRV_PCM_FMTBIT_S16,
> + .rates = SNDRV_PCM_RATE_48000,
> + .rate_min = 48000,
> + .rate_max = 48000,
> + .channels_min = 1,
> + .channels_max = 2,
> + },
> + .ops = &asoc_qcom_qaif_cif_dai_ops,
> + }, {
> + .id = RX_CODEC_DMA_RX_1,
> + .name = "RX CDC DMA RX1",
> + .playback = {
> + .stream_name = "RX CDC DMA RX1 Playback",
> + .formats = SNDRV_PCM_FMTBIT_S16,
> + .rates = SNDRV_PCM_RATE_48000,
> + .rate_min = 48000,
> + .rate_max = 48000,
> + .channels_min = 1,
> + .channels_max = 2,
> + },
> + .ops = &asoc_qcom_qaif_cif_dai_ops,
> + }, {
> + .id = VA_CODEC_DMA_TX_0,
> + .name = "VA CDC DMA TX0",
> + .capture = {
> + .stream_name = "VA CDC DMA TX0 Capture",
> + .formats = SNDRV_PCM_FMTBIT_S16,
> + .rates = SNDRV_PCM_RATE_48000,
> + .rate_min = 48000,
> + .rate_max = 48000,
> + .channels_min = 1,
> + .channels_max = 4,
> + },
> + .ops = &asoc_qcom_qaif_cif_dai_ops,
> + }, {
> + .id = VA_CODEC_DMA_TX_1,
> + .name = "VA CDC DMA TX1",
> + .capture = {
> + .stream_name = "VA CDC DMA TX1 Capture",
> + .formats = SNDRV_PCM_FMTBIT_S16,
> + .rates = SNDRV_PCM_RATE_48000,
> + .rate_min = 48000,
> + .rate_max = 48000,
> + .channels_min = 1,
> + .channels_max = 4,
> + },
> + .ops = &asoc_qcom_qaif_cif_dai_ops,
> + },
> +};
> +
> +static int shikra_qaif_get_dma_idx(unsigned int dai_id)
> +{
> + const struct qaif_dmaidx_dai_map *map;
> + int i, size;
> +
> + if (dai_id >= AIF_MI2S_RX_0 && dai_id <= AIF_MI2S_TX_12) {
> + map = shikra_mi2s_dma_dai_map;
> + size = ARRAY_SIZE(shikra_mi2s_dma_dai_map);
> + } else if (dai_id >= AIF_TDM_RX_0 && dai_id <= AIF_TDM_TX_12) {
> + map = shikra_tdm_dma_dai_map;
> + size = ARRAY_SIZE(shikra_tdm_dma_dai_map);
> + } else {
> + map = shikra_cif_dma_dai_map;
> + size = ARRAY_SIZE(shikra_cif_dma_dai_map);
> + }
> +
> + for (i = 0; i < size; i++) {
> + if (map[i].dai_id == dai_id)
> + return map[i].dma_idx;
> + }
> + return -EINVAL;
> +}
> +
> +static int shikra_qaif_alloc_stream_dma_idx(struct qaif_drv_data *drvdata,
> + int direction,
> + unsigned int dai_id)
> +{
> + const struct qaif_variant *v = drvdata->variant;
> + int dma_idx, index;
> +
> + dma_idx = shikra_qaif_get_dma_idx(dai_id);
> + if (dma_idx < 0)
> + return dma_idx;
> +
> + if (qaif_is_aif_port(dai_id)) {
> + index = (direction == SNDRV_PCM_STREAM_PLAYBACK) ?
> + dma_idx : v->wrdma_start + dma_idx;
> + if (index >= QAIF_MAX_AIF_DMA_IDX)
> + return -EINVAL;
> + if (test_and_set_bit(index, &drvdata->aif_dma_idx_bit_map))
> + return -EBUSY;
> + } else if (qaif_is_cif_port(dai_id)) {
> + index = (direction == SNDRV_PCM_STREAM_PLAYBACK) ?
> + dma_idx : v->codec_wrdma_start + dma_idx;
> + if (index >= QAIF_MAX_CIF_DMA_IDX)
> + return -EINVAL;
> + if (test_and_set_bit(index, &drvdata->cif_dma_idx_bit_map))
> + return -EBUSY;
> + } else {
> + return -EINVAL;
> + }
> +
> + return index;
> +}
> +
> +static int shikra_qaif_free_stream_dma_idx(struct qaif_drv_data *drvdata,
> + int index,
> + unsigned int dai_id)
> +{
> + if (qaif_is_aif_port(dai_id))
> + clear_bit(index, &drvdata->aif_dma_idx_bit_map);
> + else
> + clear_bit(index, &drvdata->cif_dma_idx_bit_map);
> + return 0;
> +}
> +
> +static const struct qaif_variant shikra_qaif_data = {
> + .ee = 0,
> +
> + .num_rddma = 4,
> + .num_wrdma = 4,
> + .wrdma_start = 4,
> +
> + .num_codec_rddma = 4,
> + .num_codec_wrdma = 4,
> + .codec_wrdma_start = 4,
> + .num_intf = 4,
> +
> + .rddma_reg_base = 0x8000,
> + .rddma_stride = 0x1000,
> + .codec_rddma_reg_base = 0xc000,
> + .codec_rddma_stride = 0x1000,
> +
> + .wrdma_reg_base = 0x11000,
> + .wrdma_stride = 0x1000,
> + .codec_wrdma_reg_base = 0x15000,
> + .codec_wrdma_stride = 0x1000,
> +
> + .rddma_irq_reg_base = 0x19000,
> + .rddma_irq_stride = 0x1000,
> + .codec_rddma_irq_reg_base = 0x191A0,
> + .codec_rddma_irq_stride = 0x1000,
> +
> + .wrdma_irq_reg_base = 0x19078,
> + .wrdma_irq_stride = 0x1000,
> + .codec_wrdma_irq_reg_base = 0x19290,
> + .codec_wrdma_irq_stride = 0x1000,
> +
> + .qxm_type = QAIF_QXM0,
> + .rddma_shram_len = 64,
> + .rddma_shram_start_addr = {0, 256},
> + .wrdma_shram_len = 64,
> + .wrdma_shram_start_addr = {0, 256},
> +
> + .clk_name = (const char * const []) {
> + "lpass_config",
> + "lpass_core_axim",
> + "bus",
> + },
> + .num_clks = 3,
> +
> + .dai_driver = shikra_qaif_cpu_dai_driver,
> + .num_dai = ARRAY_SIZE(shikra_qaif_cpu_dai_driver),
> +
> + .dai_bit_clk_names = (const char * const []) {
> + "aif_if0_ibit",
> + "aif_if1_ibit",
> + "aif_if2_ibit",
> + "aif_if3_ibit",
> + },
> + .aif_full_cycle_en = (const bool []) { false, false, false, false },
> + .aif_ctrl_data_oe = (const bool []) { false, false, false, false },
> + .aif_loopback_en = (const bool []) { false, false, false, false },
> + .alloc_stream_dma_idx = shikra_qaif_alloc_stream_dma_idx,
> + .free_stream_dma_idx = shikra_qaif_free_stream_dma_idx,
> + .get_dma_idx = shikra_qaif_get_dma_idx,
> +};
> +
> +static const struct of_device_id shikra_qaif_cpu_device_id[] = {
> + { .compatible = "qcom,shikra-qaif-cpu", .data = &shikra_qaif_data },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, shikra_qaif_cpu_device_id);
> +
> +static struct platform_driver shikra_qaif_cpu_platform_driver = {
> + .driver = {
> + .name = "shikra-qaif-cpu",
> + .of_match_table = shikra_qaif_cpu_device_id,
> + .pm = pm_ptr(&asoc_qcom_qaif_pm_ops),
> + },
> + .probe = asoc_qcom_qaif_cpu_platform_probe,
> +};
> +module_platform_driver(shikra_qaif_cpu_platform_driver);
> +
> +MODULE_DESCRIPTION("Qualcomm Audio Interface (QAIF) Shikra variant driver");
> +MODULE_AUTHOR("Harendra Gautam <harendra.gautam@oss.qualcomm.com>");
> +MODULE_LICENSE("GPL");
>
next prev parent reply other threads:[~2026-10-15 7:02 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-13 5:51 [PATCH v9 00/10] ASoC: qcom: Add QAIF driver for Shikra audio platform Harendra Gautam
2026-10-13 5:51 ` [PATCH v9 01/10] ASoC: dt-bindings: qcom,shikra-qaif-cpu: Add binding Harendra Gautam
2026-10-14 7:02 ` Ajay Kumar Nandam
2026-10-15 3:34 ` Rob Herring (Arm)
2026-10-13 5:51 ` [PATCH v9 02/10] ASoC: qcom: Add QAIF shared data structures and variant interface Harendra Gautam
2026-10-14 7:03 ` Ajay Kumar Nandam
2026-10-13 5:51 ` [PATCH v9 03/10] ASoC: qcom: Add QAIF hardware register map Harendra Gautam
2026-10-14 7:03 ` Ajay Kumar Nandam
2026-10-14 7:08 ` Ajay Kumar Nandam
2026-10-13 5:51 ` [PATCH v9 04/10] ASoC: qcom: Add QAIF CPU DAI ops, regmap, DT parsing and platform init Harendra Gautam
2026-10-14 7:54 ` Ajay Kumar Nandam
2026-10-15 8:48 ` Srinivas Kandagatla
2026-10-13 5:51 ` [PATCH v9 05/10] ASoC: soc-core: Add snd_soc_of_xlate_dai_name() generic helper Harendra Gautam
2026-10-15 8:58 ` Srinivas Kandagatla
2026-10-13 5:51 ` [PATCH v9 06/10] ASoC: qcom: Switch lpass-cpu and qaif-cpu to snd_soc_of_xlate_dai_name() Harendra Gautam
2026-10-13 5:51 ` [PATCH v9 07/10] ASoC: qcom: Add QAIF PCM operations Harendra Gautam
2026-10-14 7:54 ` Ajay Kumar Nandam
2026-10-15 9:23 ` Srinivas Kandagatla
2026-10-13 5:51 ` [PATCH v9 08/10] ASoC: qcom: Add QAIF IRQ handling and platform register Harendra Gautam
2026-10-15 9:41 ` Srinivas Kandagatla
2026-10-13 5:51 ` [PATCH v9 09/10] ASoC: qcom: Add Shikra QAIF support Harendra Gautam
2026-10-15 7:02 ` Ajay Kumar Nandam [this message]
2026-10-13 5:51 ` [PATCH v9 10/10] MAINTAINERS: Add Qualcomm QAIF driver entry Harendra Gautam
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