From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Julius Bairaktaris <julius@bairaktaris.de>,
Bjorn Andersson <andersson@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>, Abel Vesa <abelvesa@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Vladyslav Andreichykov <vladdrako007@gmail.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: qcom: gcc-ipq6018: add fallback names for the bias PLL parents
Date: Wed, 21 Oct 2026 10:05:58 +0200 [thread overview]
Message-ID: <3c5f973a-c97d-4a76-b357-09f8feffae28@oss.qualcomm.com> (raw)
In-Reply-To: <20261020065430.1251541-1-julius@bairaktaris.de>
On 10/20/26 8:54 AM, Julius Bairaktaris wrote:
> From: Vladyslav Andreichykov <vladdrako007@gmail.com>
>
> bias_pll_cc_clk and bias_pll_nss_noc_clk are outputs of the CMN PLL,
> which takes its AHB and SYS clocks from GCC, so the device tree does not
> pass them back to GCC. With only .fw_name these parents never resolve,
> nss_ppe_clk_src stays an orphan, and setting it to 300 MHz fails with
> -EINVAL. The NSS clocks below it, such as gcc_nss_edma_clk, read 0 Hz.
Because this is a "never could have worked" situation, we should
properly fix it by adding the DT references to those clocks. This
way we also get fw_devlink which will ensure the probe ordering
is right.
Konrad
prev parent reply other threads:[~2026-10-21 8:06 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-20 6:54 Julius Bairaktaris
2026-10-20 11:39 ` Robert Marko
2026-10-21 8:06 ` Konrad Dybcio
2026-10-21 8:05 ` Konrad Dybcio [this message]
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