[PATCH] clk: qcom: gcc-ipq6018: add fallback names for the bias PLL parents

[PATCH] clk: qcom: gcc-ipq6018: add fallback names for the bias PLL parents

[Julius Bairaktaris]

From: Vladyslav Andreichykov <vladdrako007@gmail.com>

bias_pll_cc_clk and bias_pll_nss_noc_clk are outputs of the CMN PLL,
which takes its AHB and SYS clocks from GCC, so the device tree does not
pass them back to GCC. With only .fw_name these parents never resolve,
nss_ppe_clk_src stays an orphan, and setting it to 300 MHz fails with
-EINVAL. The NSS clocks below it, such as gcc_nss_edma_clk, read 0 Hz.

Add .name fallbacks so they resolve to the clocks the CMN PLL registers,
as gcc-ipq8074 already does.

Tested-by: Vladyslav Andreichykov <vladdrako007@gmail.com>
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Vladyslav Andreichykov <vladdrako007@gmail.com>
Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de>
---
 drivers/clk/qcom/gcc-ipq6018.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
index 6943dc511534f..f58000407d015 100644
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -360,7 +360,7 @@ static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
 
 static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
 	{ .fw_name = "xo" },
-	{ .fw_name = "bias_pll_cc_clk" },
+	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
 	{ .hw = &gpll0.clkr.hw },
 	{ .hw = &gpll4.clkr.hw },
 	{ .hw = &nss_crypto_pll.clkr.hw },
@@ -539,7 +539,7 @@ gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
 	{ .fw_name = "uniphy1_gcc_rx_clk" },
 	{ .fw_name = "uniphy1_gcc_tx_clk" },
 	{ .hw = &ubi32_pll.clkr.hw },
-	{ .fw_name = "bias_pll_cc_clk" },
+	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
 };
 
 static const struct parent_map
@@ -594,7 +594,7 @@ gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
 	{ .fw_name = "uniphy1_gcc_tx_clk" },
 	{ .fw_name = "uniphy1_gcc_rx_clk" },
 	{ .hw = &ubi32_pll.clkr.hw },
-	{ .fw_name = "bias_pll_cc_clk" },
+	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
 };
 
 static const struct parent_map
@@ -733,7 +733,7 @@ static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
 	{ .fw_name = "uniphy0_gcc_rx_clk" },
 	{ .fw_name = "uniphy0_gcc_tx_clk" },
 	{ .hw = &ubi32_pll.clkr.hw },
-	{ .fw_name = "bias_pll_cc_clk" },
+	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
 };
 
 static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
@@ -769,7 +769,7 @@ static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
 	{ .fw_name = "uniphy0_gcc_tx_clk" },
 	{ .fw_name = "uniphy0_gcc_rx_clk" },
 	{ .hw = &ubi32_pll.clkr.hw },
-	{ .fw_name = "bias_pll_cc_clk" },
+	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
 };
 
 static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
@@ -1920,7 +1920,7 @@ static const struct clk_parent_data
 	{ .fw_name = "xo" },
 	{ .hw = &gpll0.clkr.hw },
 	{ .hw = &gpll2.clkr.hw },
-	{ .fw_name = "bias_pll_nss_noc_clk" },
+	{ .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
 };
 
 static const struct parent_map gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map[] = {
-- 
2.53.0

Re: [PATCH] clk: qcom: gcc-ipq6018: add fallback names for the bias PLL parents

[Robert Marko]

On 20/10/2026 08:54, Julius Bairaktaris wrote:
> From: Vladyslav Andreichykov <vladdrako007@gmail.com>
>
> bias_pll_cc_clk and bias_pll_nss_noc_clk are outputs of the CMN PLL,
> which takes its AHB and SYS clocks from GCC, so the device tree does not
> pass them back to GCC. With only .fw_name these parents never resolve,
> nss_ppe_clk_src stays an orphan, and setting it to 300 MHz fails with
> -EINVAL. The NSS clocks below it, such as gcc_nss_edma_clk, read 0 Hz.
>
> Add .name fallbacks so they resolve to the clocks the CMN PLL registers,
> as gcc-ipq8074 already does.
>
> Tested-by: Vladyslav Andreichykov <vladdrako007@gmail.com>
> Assisted-by: Claude:claude-opus-5-5
> Signed-off-by: Vladyslav Andreichykov <vladdrako007@gmail.com>
> Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de>
> ---

Hi,

This issue does not exist upstream, as CMN PLL is not yet wired due to 
missing
networking, even then the solution is not to add global name matching.

The required clock inputs should just be passed to GCC directly which I have
just pushed to OpenWrt.

Regards,
Robert

>   drivers/clk/qcom/gcc-ipq6018.c | 12 ++++++------
>   1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
> index 6943dc511534f..f58000407d015 100644
> --- a/drivers/clk/qcom/gcc-ipq6018.c
> +++ b/drivers/clk/qcom/gcc-ipq6018.c
> @@ -360,7 +360,7 @@ static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
>   
>   static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
>   	{ .fw_name = "xo" },
> -	{ .fw_name = "bias_pll_cc_clk" },
> +	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
>   	{ .hw = &gpll0.clkr.hw },
>   	{ .hw = &gpll4.clkr.hw },
>   	{ .hw = &nss_crypto_pll.clkr.hw },
> @@ -539,7 +539,7 @@ gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
>   	{ .fw_name = "uniphy1_gcc_rx_clk" },
>   	{ .fw_name = "uniphy1_gcc_tx_clk" },
>   	{ .hw = &ubi32_pll.clkr.hw },
> -	{ .fw_name = "bias_pll_cc_clk" },
> +	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
>   };
>   
>   static const struct parent_map
> @@ -594,7 +594,7 @@ gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
>   	{ .fw_name = "uniphy1_gcc_tx_clk" },
>   	{ .fw_name = "uniphy1_gcc_rx_clk" },
>   	{ .hw = &ubi32_pll.clkr.hw },
> -	{ .fw_name = "bias_pll_cc_clk" },
> +	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
>   };
>   
>   static const struct parent_map
> @@ -733,7 +733,7 @@ static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
>   	{ .fw_name = "uniphy0_gcc_rx_clk" },
>   	{ .fw_name = "uniphy0_gcc_tx_clk" },
>   	{ .hw = &ubi32_pll.clkr.hw },
> -	{ .fw_name = "bias_pll_cc_clk" },
> +	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
>   };
>   
>   static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
> @@ -769,7 +769,7 @@ static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
>   	{ .fw_name = "uniphy0_gcc_tx_clk" },
>   	{ .fw_name = "uniphy0_gcc_rx_clk" },
>   	{ .hw = &ubi32_pll.clkr.hw },
> -	{ .fw_name = "bias_pll_cc_clk" },
> +	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
>   };
>   
>   static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
> @@ -1920,7 +1920,7 @@ static const struct clk_parent_data
>   	{ .fw_name = "xo" },
>   	{ .hw = &gpll0.clkr.hw },
>   	{ .hw = &gpll2.clkr.hw },
> -	{ .fw_name = "bias_pll_nss_noc_clk" },
> +	{ .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
>   };
>   
>   static const struct parent_map gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map[] = {

Re: [PATCH] clk: qcom: gcc-ipq6018: add fallback names for the bias PLL parents

[Konrad Dybcio]

On 10/20/26 1:39 PM, Robert Marko wrote:
> 
> On 20/10/2026 08:54, Julius Bairaktaris wrote:
>> From: Vladyslav Andreichykov <vladdrako007@gmail.com>
>>
>> bias_pll_cc_clk and bias_pll_nss_noc_clk are outputs of the CMN PLL,
>> which takes its AHB and SYS clocks from GCC, so the device tree does not
>> pass them back to GCC. With only .fw_name these parents never resolve,
>> nss_ppe_clk_src stays an orphan, and setting it to 300 MHz fails with
>> -EINVAL. The NSS clocks below it, such as gcc_nss_edma_clk, read 0 Hz.
>>
>> Add .name fallbacks so they resolve to the clocks the CMN PLL registers,
>> as gcc-ipq8074 already does.
>>
>> Tested-by: Vladyslav Andreichykov <vladdrako007@gmail.com>
>> Assisted-by: Claude:claude-opus-5-5
>> Signed-off-by: Vladyslav Andreichykov <vladdrako007@gmail.com>
>> Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de>
>> ---
> 
> Hi,
> 
> This issue does not exist upstream, as CMN PLL is not yet wired due to missing
> networking, even then the solution is not to add global name matching.
> 
> The required clock inputs should just be passed to GCC directly which I have
> just pushed to OpenWrt.

Just read your reply after writing mine, I'm looking forward to seeing
that patch!

Konrad

Re: [PATCH] clk: qcom: gcc-ipq6018: add fallback names for the bias PLL parents

[Konrad Dybcio]

On 10/20/26 8:54 AM, Julius Bairaktaris wrote:
> From: Vladyslav Andreichykov <vladdrako007@gmail.com>
> 
> bias_pll_cc_clk and bias_pll_nss_noc_clk are outputs of the CMN PLL,
> which takes its AHB and SYS clocks from GCC, so the device tree does not
> pass them back to GCC. With only .fw_name these parents never resolve,
> nss_ppe_clk_src stays an orphan, and setting it to 300 MHz fails with
> -EINVAL. The NSS clocks below it, such as gcc_nss_edma_clk, read 0 Hz.

Because this is a "never could have worked" situation, we should
properly fix it by adding the DT references to those clocks. This
way we also get fw_devlink which will ensure the probe ordering
is right.

Konrad