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From: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: <vkoul@kernel.org>, <kishon@kernel.org>, <konradybcio@kernel.org>,
	<andersson@kernel.org>, <simona@ffwll.ch>, <abel.vesa@linaro.org>,
	<robdclark@gmail.com>, <quic_abhinavk@quicinc.com>,
	<sean@poorly.run>, <marijn.suijten@somainline.org>,
	<airlied@gmail.com>, <daniel@ffwll.ch>,
	<maarten.lankhorst@linux.intel.com>, <mripard@kernel.org>,
	<tzimmermann@suse.de>, <robh@kernel.org>, <krzk+dt@kernel.org>,
	<conor+dt@kernel.org>, <quic_khsieh@quicinc.com>,
	<konrad.dybcio@linaro.org>, <quic_parellan@quicinc.com>,
	<quic_bjorande@quicinc.com>, <linux-arm-msm@vger.kernel.org>,
	<linux-phy@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<dri-devel@lists.freedesktop.org>,
	<freedreno@lists.freedesktop.org>, <devicetree@vger.kernel.org>,
	<quic_riteshk@quicinc.com>, <quic_vproddut@quicinc.com>
Subject: Re: [PATCH v2 2/5] phy: qcom: edp: Introduce aux_cfg array for version specific aux settings
Date: Tue, 17 Sep 2024 14:10:10 +0530	[thread overview]
Message-ID: <3ea1189b-8b06-45bb-9d60-178f69ee407d@quicinc.com> (raw)
In-Reply-To: <CAA8EJppddLmzJ9WSkLLr-nwM-qe647Sm6jV8SpHdB=0vRQT-=Q@mail.gmail.com>


On 9/13/2024 5:12 PM, Dmitry Baryshkov wrote:
> On Fri, 13 Sept 2024 at 13:38, Soutrik Mukhopadhyay
> <quic_mukhopad@quicinc.com> wrote:
>> In order to support different HW versions, introduce aux_cfg array
>> to move v4 specific aux configuration settings.
>>
>> Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
>> ---
>> v2: Fixed review comments from Bjorn and Dmitry
>>          - Made aux_cfg array as const.
>>
>> ---
>>   drivers/phy/qualcomm/phy-qcom-edp.c | 37 ++++++++++++++++++-----------
>>   1 file changed, 23 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c
>> index da2b32fb5b45..bcd5aced9e06 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-edp.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-edp.c
>> @@ -90,6 +90,7 @@ struct phy_ver_ops {
>>
>>   struct qcom_edp_phy_cfg {
>>          bool is_edp;
>> +       const u8 *aux_cfg;
>>          const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg;
>>          const struct phy_ver_ops *ver_ops;
>>   };
>> @@ -186,11 +187,15 @@ static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg = {
>>          .pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3,
>>   };
>>
>> +static const u8 edp_phy_aux_cfg_v4[10] = {
>> +       0x00, 0x13, 0x24, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03
>> +};
>> +
>>   static int qcom_edp_phy_init(struct phy *phy)
>>   {
>>          struct qcom_edp *edp = phy_get_drvdata(phy);
>> +       u8 aux_cfg[10];
> Please define 10, so that there are no magic numbers (and less chance
> of damaging the stack if it gets changed in one place only.


Sure, we will update this in the next version.


>
>>          int ret;
>> -       u8 cfg8;
>>
>>          ret = regulator_bulk_enable(ARRAY_SIZE(edp->supplies), edp->supplies);
>>          if (ret)
>> @@ -200,6 +205,8 @@ static int qcom_edp_phy_init(struct phy *phy)
>>          if (ret)
>>                  goto out_disable_supplies;
>>
>> +       memcpy(aux_cfg, edp->cfg->aux_cfg, sizeof(aux_cfg));
>> +
>>          writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
>>                 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
>>                 edp->edp + DP_PHY_PD_CTL);
>> @@ -222,22 +229,20 @@ static int qcom_edp_phy_init(struct phy *phy)
>>           * even needed.
>>           */
>>          if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp)
>> -               cfg8 = 0xb7;
>> -       else
>> -               cfg8 = 0x37;
>> +               aux_cfg[8] = 0xb7;
>>
>>          writel(0xfc, edp->edp + DP_PHY_MODE);
>>
>> -       writel(0x00, edp->edp + DP_PHY_AUX_CFG0);
>> -       writel(0x13, edp->edp + DP_PHY_AUX_CFG1);
>> -       writel(0x24, edp->edp + DP_PHY_AUX_CFG2);
>> -       writel(0x00, edp->edp + DP_PHY_AUX_CFG3);
>> -       writel(0x0a, edp->edp + DP_PHY_AUX_CFG4);
>> -       writel(0x26, edp->edp + DP_PHY_AUX_CFG5);
>> -       writel(0x0a, edp->edp + DP_PHY_AUX_CFG6);
>> -       writel(0x03, edp->edp + DP_PHY_AUX_CFG7);
>> -       writel(cfg8, edp->edp + DP_PHY_AUX_CFG8);
>> -       writel(0x03, edp->edp + DP_PHY_AUX_CFG9);
>> +       writel(aux_cfg[0], edp->edp + DP_PHY_AUX_CFG0);
>> +       writel(aux_cfg[1], edp->edp + DP_PHY_AUX_CFG1);
>> +       writel(aux_cfg[2], edp->edp + DP_PHY_AUX_CFG2);
>> +       writel(aux_cfg[3], edp->edp + DP_PHY_AUX_CFG3);
>> +       writel(aux_cfg[4], edp->edp + DP_PHY_AUX_CFG4);
>> +       writel(aux_cfg[5], edp->edp + DP_PHY_AUX_CFG5);
>> +       writel(aux_cfg[6], edp->edp + DP_PHY_AUX_CFG6);
>> +       writel(aux_cfg[7], edp->edp + DP_PHY_AUX_CFG7);
>> +       writel(aux_cfg[8], edp->edp + DP_PHY_AUX_CFG8);
>> +       writel(aux_cfg[9], edp->edp + DP_PHY_AUX_CFG9);
> Replace this with a loop?


Can we use below approach for this :

#define DP_PHY_AUX_CFG(n)        (0x24 + (0x04 * (n)))

for (int i = 0; i < 10; i++)

     writel(aux_cfg[i], edp->edp + DP_PHY_AUX_CFG(i));


>
>>          writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
>>                 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
>> @@ -519,16 +524,19 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 = {
>>   };
>>
>>   static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = {
>> +       .aux_cfg = edp_phy_aux_cfg_v4,
>>          .ver_ops = &qcom_edp_phy_ops_v4,
>>   };
>>
>>   static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg = {
>> +       .aux_cfg = edp_phy_aux_cfg_v4,
>>          .swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,
>>          .ver_ops = &qcom_edp_phy_ops_v4,
>>   };
>>
>>   static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg = {
>>          .is_edp = true,
>> +       .aux_cfg = edp_phy_aux_cfg_v4,
>>          .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,
>>          .ver_ops = &qcom_edp_phy_ops_v4,
>>   };
>> @@ -707,6 +715,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v6 = {
>>   };
>>
>>   static struct qcom_edp_phy_cfg x1e80100_phy_cfg = {
>> +       .aux_cfg = edp_phy_aux_cfg_v4,
>>          .swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,
>>          .ver_ops = &qcom_edp_phy_ops_v6,
>>   };
>> --
>> 2.17.1
>>
>

  reply	other threads:[~2024-09-17  8:40 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-13 10:37 [PATCH v2 0/5] Add support for DisplayPort on SA8775P platform Soutrik Mukhopadhyay
2024-09-13 10:37 ` [PATCH v2 1/5] dt-bindings: phy: Add eDP PHY compatible for sa8775p Soutrik Mukhopadhyay
2024-09-16 15:21   ` Krzysztof Kozlowski
2024-09-16 15:23   ` Krzysztof Kozlowski
2024-09-16 20:33     ` Dmitry Baryshkov
2024-09-16 23:26       ` Konrad Dybcio
2024-09-17  6:04         ` Krzysztof Kozlowski
2024-09-13 10:37 ` [PATCH v2 2/5] phy: qcom: edp: Introduce aux_cfg array for version specific aux settings Soutrik Mukhopadhyay
2024-09-13 11:42   ` Dmitry Baryshkov
2024-09-17  8:40     ` Soutrik Mukhopadhyay [this message]
2024-09-17  9:41       ` Dmitry Baryshkov
2024-09-14 11:29   ` Konrad Dybcio
2024-09-14 12:04     ` Dmitry Baryshkov
2024-09-13 10:37 ` [PATCH v2 3/5] phy: qcom: edp: Add support for eDP PHY on SA8775P Soutrik Mukhopadhyay
2024-09-13 12:35   ` Dmitry Baryshkov
2024-09-13 10:37 ` [PATCH v2 4/5] dt-bindings: display: msm: dp-controller: document SA8775P compatible Soutrik Mukhopadhyay
2024-09-13 10:37 ` [PATCH v2 5/5] drm/msm/dp: Add DisplayPort controller for SA8775P Soutrik Mukhopadhyay
2024-09-13 11:44   ` Dmitry Baryshkov

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