* [PATCH 0/5] A621 support
@ 2024-07-19 10:03 Konrad Dybcio
2024-07-19 10:03 ` [PATCH 1/5] drm/msm/a6xx: Evaluate adreno_is_a650_family in pdc_in_aop check Konrad Dybcio
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Konrad Dybcio @ 2024-07-19 10:03 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Dmitry Baryshkov,
David Airlie, Daniel Vetter
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno,
linux-kernel, Konrad Dybcio
Baby A650, needs mesa mr !30253 (or better)
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Konrad Dybcio (5):
drm/msm/a6xx: Evaluate adreno_is_a650_family in pdc_in_aop check
drm/msm/a6xx: Store primFifoThreshold in struct a6xx_info
drm/msm/a6xx: Store gmu_cgc_mode in struct a6xx_info
drm/msm/a6xx: Set GMU CGC properties on a6xx too
drm/msm/a6xx: Add A621 support
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 111 +++++++++++++++++++++++++++++-
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 21 +++++-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 52 ++++++--------
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 13 +++-
5 files changed, 164 insertions(+), 35 deletions(-)
---
base-commit: 797012914d2d031430268fe512af0ccd7d8e46ef
change-id: 20240719-topic-a621-b5e83f79b4f7
Best regards,
--
Konrad Dybcio <konrad.dybcio@linaro.org>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/5] drm/msm/a6xx: Evaluate adreno_is_a650_family in pdc_in_aop check
2024-07-19 10:03 [PATCH 0/5] A621 support Konrad Dybcio
@ 2024-07-19 10:03 ` Konrad Dybcio
2024-07-19 10:03 ` [PATCH 2/5] drm/msm/a6xx: Store primFifoThreshold in struct a6xx_info Konrad Dybcio
` (3 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Konrad Dybcio @ 2024-07-19 10:03 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Dmitry Baryshkov,
David Airlie, Daniel Vetter
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno,
linux-kernel, Konrad Dybcio
A650 family includes A660 family (they've got a big family), A650
itself, and some more A6XX_GEN3 SKUs, all of which should fall into
the same branch of the if-condition. Simplify that.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index cb538a262d1c..6f168f1f32d8 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -525,8 +525,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
if (IS_ERR(pdcptr))
goto err;
- if (adreno_is_a650(adreno_gpu) ||
- adreno_is_a660_family(adreno_gpu) ||
+ if (adreno_is_a650_family(adreno_gpu) ||
adreno_is_a7xx(adreno_gpu))
pdc_in_aop = true;
else if (adreno_is_a618(adreno_gpu) || adreno_is_a640_family(adreno_gpu))
--
2.45.2
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/5] drm/msm/a6xx: Store primFifoThreshold in struct a6xx_info
2024-07-19 10:03 [PATCH 0/5] A621 support Konrad Dybcio
2024-07-19 10:03 ` [PATCH 1/5] drm/msm/a6xx: Evaluate adreno_is_a650_family in pdc_in_aop check Konrad Dybcio
@ 2024-07-19 10:03 ` Konrad Dybcio
2024-07-19 10:03 ` [PATCH 3/5] drm/msm/a6xx: Store gmu_cgc_mode " Konrad Dybcio
` (2 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Konrad Dybcio @ 2024-07-19 10:03 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Dmitry Baryshkov,
David Airlie, Daniel Vetter
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno,
linux-kernel, Konrad Dybcio
The if-else monster is so unmaintainable that one case is repeated
twice. Get rid of it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 14 ++++++++++++++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 24 +++++-------------------
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
3 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 68ba9aed5506..1ea535960f32 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -636,6 +636,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a612_hwcg,
.protect = &a630_protect,
+ .prim_fifo_threshold = 0x00080000,
},
/*
* There are (at least) three SoCs implementing A610: SM6125
@@ -667,6 +668,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a615_hwcg,
.protect = &a630_protect,
+ .prim_fifo_threshold = 0x00180000,
},
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
@@ -689,6 +691,7 @@ static const struct adreno_info a6xx_gpus[] = {
.init = a6xx_gpu_init,
.a6xx = &(const struct a6xx_info) {
.protect = &a630_protect,
+ .prim_fifo_threshold = 0x00180000,
},
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
@@ -711,6 +714,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a615_hwcg,
.protect = &a630_protect,
+ .prim_fifo_threshold = 0x00018000,
},
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
@@ -733,6 +737,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a615_hwcg,
.protect = &a630_protect,
+ .prim_fifo_threshold = 0x00018000,
},
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
@@ -755,6 +760,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a615_hwcg,
.protect = &a630_protect,
+ .prim_fifo_threshold = 0x00018000,
},
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
@@ -782,6 +788,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a630_hwcg,
.protect = &a630_protect,
+ .prim_fifo_threshold = 0x00180000,
},
}, {
.chip_ids = ADRENO_CHIP_IDS(0x06040001),
@@ -799,6 +806,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a640_hwcg,
.protect = &a630_protect,
+ .prim_fifo_threshold = 0x00180000,
},
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
@@ -821,6 +829,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a650_hwcg,
.protect = &a650_protect,
+ .prim_fifo_threshold = 0x00300200,
},
.address_space_size = SZ_16G,
.speedbins = ADRENO_SPEEDBINS(
@@ -846,6 +855,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a660_hwcg,
.protect = &a660_protect,
+ .prim_fifo_threshold = 0x00300200,
},
.address_space_size = SZ_16G,
}, {
@@ -864,6 +874,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a660_hwcg,
.protect = &a660_protect,
+ .prim_fifo_threshold = 0x00200200,
},
.address_space_size = SZ_16G,
.speedbins = ADRENO_SPEEDBINS(
@@ -888,6 +899,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a640_hwcg,
.protect = &a630_protect,
+ .prim_fifo_threshold = 0x00200200,
},
}, {
.chip_ids = ADRENO_CHIP_IDS(0x06090000),
@@ -905,6 +917,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a690_hwcg,
.protect = &a690_protect,
+ .prim_fifo_threshold = 0x00800200,
},
.address_space_size = SZ_16G,
}
@@ -1165,6 +1178,7 @@ static const struct adreno_info a7xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a702_hwcg,
.protect = &a650_protect,
+ .prim_fifo_threshold = 0x0000c000,
},
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index bcaec86ac67a..aaeb1161f90d 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -976,25 +976,11 @@ static int hw_init(struct msm_gpu *gpu)
} else if (!adreno_is_a7xx(adreno_gpu))
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
- /* Setting the primFifo thresholds default values,
- * and vccCacheSkipDis=1 bit (0x200) for A640 and newer
- */
- if (adreno_is_a702(adreno_gpu))
- gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x0000c000);
- else if (adreno_is_a690(adreno_gpu))
- gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00800200);
- else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
- gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
- else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu))
- gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
- else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
- gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
- else if (adreno_is_a619(adreno_gpu))
- gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00018000);
- else if (adreno_is_a610(adreno_gpu))
- gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000);
- else if (!adreno_is_a7xx(adreno_gpu))
- gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000);
+
+ /* Set the default primFifo threshold values */
+ if (adreno_gpu->info->a6xx->prim_fifo_threshold)
+ gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL,
+ adreno_gpu->info->a6xx->prim_fifo_threshold);
/* Set the AHB default slave response to "ERROR" */
gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index e3e5c53ae8af..bc37bd8c7f65 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -22,6 +22,7 @@ struct a6xx_info {
const struct adreno_reglist *hwcg;
const struct adreno_protect *protect;
u32 gmu_chipid;
+ u32 prim_fifo_threshold;
};
struct a6xx_gpu {
--
2.45.2
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/5] drm/msm/a6xx: Store gmu_cgc_mode in struct a6xx_info
2024-07-19 10:03 [PATCH 0/5] A621 support Konrad Dybcio
2024-07-19 10:03 ` [PATCH 1/5] drm/msm/a6xx: Evaluate adreno_is_a650_family in pdc_in_aop check Konrad Dybcio
2024-07-19 10:03 ` [PATCH 2/5] drm/msm/a6xx: Store primFifoThreshold in struct a6xx_info Konrad Dybcio
@ 2024-07-19 10:03 ` Konrad Dybcio
2024-08-26 21:07 ` Rob Clark
2024-07-19 10:03 ` [PATCH 4/5] drm/msm/a6xx: Set GMU CGC properties on a6xx too Konrad Dybcio
2024-07-19 10:03 ` [PATCH 5/5] drm/msm/a6xx: Add A621 support Konrad Dybcio
4 siblings, 1 reply; 11+ messages in thread
From: Konrad Dybcio @ 2024-07-19 10:03 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Dmitry Baryshkov,
David Airlie, Daniel Vetter
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno,
linux-kernel, Konrad Dybcio
This was apparently almost never set on a6xx.. move the existing values
and fill out the remaining ones within the catalog.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 19 ++++++++++++++++++-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++----
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
3 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 1ea535960f32..deee0b686962 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -448,7 +448,6 @@ static const struct adreno_reglist a690_hwcg[] = {
{REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
{REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
{REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
- {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
{REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
{REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
{}
@@ -636,6 +635,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a612_hwcg,
.protect = &a630_protect,
+ .gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x00080000,
},
/*
@@ -668,6 +668,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a615_hwcg,
.protect = &a630_protect,
+ .gmu_cgc_mode = 0x00000222,
.prim_fifo_threshold = 0x00180000,
},
.speedbins = ADRENO_SPEEDBINS(
@@ -691,6 +692,7 @@ static const struct adreno_info a6xx_gpus[] = {
.init = a6xx_gpu_init,
.a6xx = &(const struct a6xx_info) {
.protect = &a630_protect,
+ .gmu_cgc_mode = 0x00000222,
.prim_fifo_threshold = 0x00180000,
},
.speedbins = ADRENO_SPEEDBINS(
@@ -714,6 +716,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a615_hwcg,
.protect = &a630_protect,
+ .gmu_cgc_mode = 0x00000222,
.prim_fifo_threshold = 0x00018000,
},
.speedbins = ADRENO_SPEEDBINS(
@@ -737,6 +740,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a615_hwcg,
.protect = &a630_protect,
+ .gmu_cgc_mode = 0x00000222,
.prim_fifo_threshold = 0x00018000,
},
.speedbins = ADRENO_SPEEDBINS(
@@ -760,6 +764,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a615_hwcg,
.protect = &a630_protect,
+ .gmu_cgc_mode = 0x00000222,
.prim_fifo_threshold = 0x00018000,
},
.speedbins = ADRENO_SPEEDBINS(
@@ -788,6 +793,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a630_hwcg,
.protect = &a630_protect,
+ .gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x00180000,
},
}, {
@@ -806,6 +812,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a640_hwcg,
.protect = &a630_protect,
+ .gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x00180000,
},
.speedbins = ADRENO_SPEEDBINS(
@@ -829,6 +836,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a650_hwcg,
.protect = &a650_protect,
+ .gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x00300200,
},
.address_space_size = SZ_16G,
@@ -855,6 +863,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a660_hwcg,
.protect = &a660_protect,
+ .gmu_cgc_mode = 0x00020000,
.prim_fifo_threshold = 0x00300200,
},
.address_space_size = SZ_16G,
@@ -874,6 +883,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a660_hwcg,
.protect = &a660_protect,
+ .gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x00200200,
},
.address_space_size = SZ_16G,
@@ -899,6 +909,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a640_hwcg,
.protect = &a630_protect,
+ .gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x00200200,
},
}, {
@@ -917,6 +928,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a690_hwcg,
.protect = &a690_protect,
+ .gmu_cgc_mode = 0x00020200,
.prim_fifo_threshold = 0x00800200,
},
.address_space_size = SZ_16G,
@@ -1178,6 +1190,7 @@ static const struct adreno_info a7xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a702_hwcg,
.protect = &a650_protect,
+ .gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x0000c000,
},
.speedbins = ADRENO_SPEEDBINS(
@@ -1202,6 +1215,7 @@ static const struct adreno_info a7xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a730_hwcg,
.protect = &a730_protect,
+ .gmu_cgc_mode = 0x00020000,
},
.address_space_size = SZ_16G,
}, {
@@ -1221,6 +1235,7 @@ static const struct adreno_info a7xx_gpus[] = {
.hwcg = a740_hwcg,
.protect = &a730_protect,
.gmu_chipid = 0x7020100,
+ .gmu_cgc_mode = 0x00020202,
},
.address_space_size = SZ_16G,
}, {
@@ -1239,6 +1254,7 @@ static const struct adreno_info a7xx_gpus[] = {
.hwcg = a740_hwcg,
.protect = &a730_protect,
.gmu_chipid = 0x7050001,
+ .gmu_cgc_mode = 0x00020202,
},
.address_space_size = SZ_256G,
}, {
@@ -1257,6 +1273,7 @@ static const struct adreno_info a7xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.protect = &a730_protect,
.gmu_chipid = 0x7090100,
+ .gmu_cgc_mode = 0x00020202,
},
.address_space_size = SZ_16G,
}
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index aaeb1161f90d..871452daa189 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -402,7 +402,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
const struct adreno_reglist *reg;
unsigned int i;
- u32 val, clock_cntl_on, cgc_mode;
+ u32 val, clock_cntl_on;
if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu)))
return;
@@ -417,10 +417,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
clock_cntl_on = 0x8aa8aa82;
if (adreno_is_a7xx(adreno_gpu)) {
- cgc_mode = adreno_is_a740_family(adreno_gpu) ? 0x20222 : 0x20000;
-
gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
- state ? cgc_mode : 0);
+ state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
state ? 0x10111 : 0);
gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index bc37bd8c7f65..0fb7febf70e7 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -22,6 +22,7 @@ struct a6xx_info {
const struct adreno_reglist *hwcg;
const struct adreno_protect *protect;
u32 gmu_chipid;
+ u32 gmu_cgc_mode;
u32 prim_fifo_threshold;
};
--
2.45.2
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 4/5] drm/msm/a6xx: Set GMU CGC properties on a6xx too
2024-07-19 10:03 [PATCH 0/5] A621 support Konrad Dybcio
` (2 preceding siblings ...)
2024-07-19 10:03 ` [PATCH 3/5] drm/msm/a6xx: Store gmu_cgc_mode " Konrad Dybcio
@ 2024-07-19 10:03 ` Konrad Dybcio
2024-07-19 10:03 ` [PATCH 5/5] drm/msm/a6xx: Add A621 support Konrad Dybcio
4 siblings, 0 replies; 11+ messages in thread
From: Konrad Dybcio @ 2024-07-19 10:03 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Dmitry Baryshkov,
David Airlie, Daniel Vetter
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno,
linux-kernel, Konrad Dybcio
This was apparently never done before.. Program the expected values.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 ++++++++++--------
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 8 +++++++-
2 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 871452daa189..33a319f7d200 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -402,6 +402,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
const struct adreno_reglist *reg;
unsigned int i;
+ u32 cgc_delay, cgc_hyst;
u32 val, clock_cntl_on;
if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu)))
@@ -416,14 +417,15 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
else
clock_cntl_on = 0x8aa8aa82;
- if (adreno_is_a7xx(adreno_gpu)) {
- gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
- state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
- gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
- state ? 0x10111 : 0);
- gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,
- state ? 0x5555 : 0);
- }
+ cgc_delay = adreno_is_a615_family(adreno_gpu) ? 0x111 : 0x10111;
+ cgc_hyst = adreno_is_a615_family(adreno_gpu) ? 0x555 : 0x5555;
+
+ gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
+ state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
+ gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
+ state ? cgc_delay : 0);
+ gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,
+ state ? cgc_hyst : 0);
if (!adreno_gpu->info->a6xx->hwcg) {
gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 1ab523a163a0..26972b2cc896 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -433,7 +433,13 @@ static inline int adreno_is_a610_family(const struct adreno_gpu *gpu)
return adreno_is_a610(gpu) || adreno_is_a702(gpu);
}
-/* check for a615, a616, a618, a619 or any a630 derivatives */
+/* TODO: 615/616 */
+static inline int adreno_is_a615_family(const struct adreno_gpu *gpu)
+{
+ return adreno_is_a618(gpu) ||
+ adreno_is_a619(gpu);
+}
+
static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
{
if (WARN_ON_ONCE(!gpu->info))
--
2.45.2
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 5/5] drm/msm/a6xx: Add A621 support
2024-07-19 10:03 [PATCH 0/5] A621 support Konrad Dybcio
` (3 preceding siblings ...)
2024-07-19 10:03 ` [PATCH 4/5] drm/msm/a6xx: Set GMU CGC properties on a6xx too Konrad Dybcio
@ 2024-07-19 10:03 ` Konrad Dybcio
4 siblings, 0 replies; 11+ messages in thread
From: Konrad Dybcio @ 2024-07-19 10:03 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Dmitry Baryshkov,
David Airlie, Daniel Vetter
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno,
linux-kernel, Konrad Dybcio
A621 is a clear A662 derivative (same lineage as A650), no explosions
or sick features, other than a NoC bug which can stall the GPU..
Add support for it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 78 ++++++++++++++++++++++++++++++-
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 18 +++++++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 ++
4 files changed, 106 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index deee0b686962..d9d4a3e821f7 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -129,6 +129,59 @@ static const struct adreno_reglist a615_hwcg[] = {
{},
};
+static const struct adreno_reglist a620_hwcg[] = {
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+ {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+ {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+ {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+ {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
+ {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+ {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+ {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
+ {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
+ {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+ {},
+};
+
static const struct adreno_reglist a630_hwcg[] = {
{REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
{REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
@@ -490,7 +543,6 @@ static const u32 a630_protect_regs[] = {
};
DECLARE_ADRENO_PROTECT(a630_protect, 32);
-/* These are for a620 and a650 */
static const u32 a650_protect_regs[] = {
A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
A6XX_PROTECT_RDONLY(0x00501, 0x0005),
@@ -774,6 +826,30 @@ static const struct adreno_info a6xx_gpus[] = {
{ 169, 2 },
{ 180, 1 },
),
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x06020100),
+ .family = ADRENO_6XX_GEN3,
+ .fw = {
+ [ADRENO_FW_SQE] = "a650_sqe.fw",
+ [ADRENO_FW_GMU] = "a621_gmu.bin",
+ },
+ .gmem = SZ_512K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+ ADRENO_QUIRK_HAS_HW_APRIV,
+ .init = a6xx_gpu_init,
+ .zapfw = "a620_zap.mbn",
+ .a6xx = &(const struct a6xx_info) {
+ .hwcg = a620_hwcg,
+ .protect = &a650_protect,
+ .gmu_cgc_mode = 0x00020200,
+ .prim_fifo_threshold = 0x00010000,
+ },
+ .address_space_size = SZ_16G,
+ .speedbins = ADRENO_SPEEDBINS(
+ { 0, 0 },
+ { 137, 1 },
+ ),
}, {
.chip_ids = ADRENO_CHIP_IDS(
0x06030001,
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 6f168f1f32d8..37927bdd6fbe 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -423,6 +423,20 @@ static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu)
return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
}
+static void a6xx_gemnoc_workaround(struct a6xx_gmu *gmu)
+{
+ struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
+ struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+
+ /*
+ * GEMNoC can power collapse whilst the GPU is being powered down, resulting
+ * in the power down sequence not being fully executed. That in turn can
+ * prevent CX_GDSC from collapsing. Assert Qactive to avoid this.
+ */
+ if (adreno_is_a621(adreno_gpu) || adreno_is_7c3(adreno_gpu))
+ gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, BIT(0));
+}
+
/* Let the GMU know that we are about to go into slumber */
static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu)
{
@@ -456,6 +470,8 @@ static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu)
}
out:
+ a6xx_gemnoc_workaround(gmu);
+
/* Put fence into allow mode */
gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
return ret;
@@ -945,6 +961,8 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
/* Force off SPTP in case the GMU is managing it */
a6xx_sptprac_disable(gmu);
+ a6xx_gemnoc_workaround(gmu);
+
/* Make sure there are no outstanding RPMh votes */
a6xx_gmu_rpmh_off(gmu);
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 33a319f7d200..f2eca69613af 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -523,6 +523,12 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
if (adreno_is_a619_holi(gpu))
gpu->ubwc_config.highest_bank_bit = 13;
+ if (adreno_is_a621(gpu)) {
+ gpu->ubwc_config.highest_bank_bit = 13;
+ gpu->ubwc_config.amsbc = 1;
+ gpu->ubwc_config.uavflagprd_inv = 2;
+ }
+
if (adreno_is_a640_family(gpu))
gpu->ubwc_config.amsbc = 1;
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 26972b2cc896..ea2c25e007eb 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -384,6 +384,11 @@ static inline int adreno_is_a619_holi(const struct adreno_gpu *gpu)
return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu);
}
+static inline int adreno_is_a621(const struct adreno_gpu *gpu)
+{
+ return gpu->info->chip_ids[0] == 0x06020100;
+}
+
static inline int adreno_is_a630(const struct adreno_gpu *gpu)
{
return adreno_is_revn(gpu, 630);
--
2.45.2
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/5] drm/msm/a6xx: Store gmu_cgc_mode in struct a6xx_info
2024-07-19 10:03 ` [PATCH 3/5] drm/msm/a6xx: Store gmu_cgc_mode " Konrad Dybcio
@ 2024-08-26 21:07 ` Rob Clark
2024-08-26 21:09 ` Rob Clark
0 siblings, 1 reply; 11+ messages in thread
From: Rob Clark @ 2024-08-26 21:07 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Sean Paul, Abhinav Kumar, Dmitry Baryshkov, David Airlie,
Daniel Vetter, Marijn Suijten, linux-arm-msm, dri-devel,
freedreno, linux-kernel
On Fri, Jul 19, 2024 at 3:03 AM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
> This was apparently almost never set on a6xx.. move the existing values
> and fill out the remaining ones within the catalog.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 19 ++++++++++++++++++-
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++----
> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
> 3 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 1ea535960f32..deee0b686962 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -448,7 +448,6 @@ static const struct adreno_reglist a690_hwcg[] = {
> {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
> {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
> {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
> - {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
> {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
> {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
> {}
> @@ -636,6 +635,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a612_hwcg,
> .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00020202,
> .prim_fifo_threshold = 0x00080000,
> },
> /*
> @@ -668,6 +668,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a615_hwcg,
> .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00000222,
> .prim_fifo_threshold = 0x00180000,
> },
> .speedbins = ADRENO_SPEEDBINS(
> @@ -691,6 +692,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .init = a6xx_gpu_init,
> .a6xx = &(const struct a6xx_info) {
> .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00000222,
> .prim_fifo_threshold = 0x00180000,
> },
> .speedbins = ADRENO_SPEEDBINS(
> @@ -714,6 +716,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a615_hwcg,
> .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00000222,
> .prim_fifo_threshold = 0x00018000,
> },
> .speedbins = ADRENO_SPEEDBINS(
> @@ -737,6 +740,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a615_hwcg,
> .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00000222,
> .prim_fifo_threshold = 0x00018000,
> },
> .speedbins = ADRENO_SPEEDBINS(
> @@ -760,6 +764,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a615_hwcg,
> .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00000222,
> .prim_fifo_threshold = 0x00018000,
> },
> .speedbins = ADRENO_SPEEDBINS(
> @@ -788,6 +793,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a630_hwcg,
> .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00020202,
> .prim_fifo_threshold = 0x00180000,
> },
> }, {
> @@ -806,6 +812,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a640_hwcg,
> .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00020202,
> .prim_fifo_threshold = 0x00180000,
> },
> .speedbins = ADRENO_SPEEDBINS(
> @@ -829,6 +836,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a650_hwcg,
> .protect = &a650_protect,
> + .gmu_cgc_mode = 0x00020202,
> .prim_fifo_threshold = 0x00300200,
> },
> .address_space_size = SZ_16G,
> @@ -855,6 +863,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a660_hwcg,
> .protect = &a660_protect,
> + .gmu_cgc_mode = 0x00020000,
> .prim_fifo_threshold = 0x00300200,
> },
> .address_space_size = SZ_16G,
> @@ -874,6 +883,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a660_hwcg,
> .protect = &a660_protect,
> + .gmu_cgc_mode = 0x00020202,
> .prim_fifo_threshold = 0x00200200,
> },
> .address_space_size = SZ_16G,
> @@ -899,6 +909,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a640_hwcg,
> .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00020202,
> .prim_fifo_threshold = 0x00200200,
> },
> }, {
> @@ -917,6 +928,7 @@ static const struct adreno_info a6xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a690_hwcg,
> .protect = &a690_protect,
> + .gmu_cgc_mode = 0x00020200,
> .prim_fifo_threshold = 0x00800200,
> },
> .address_space_size = SZ_16G,
> @@ -1178,6 +1190,7 @@ static const struct adreno_info a7xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a702_hwcg,
> .protect = &a650_protect,
> + .gmu_cgc_mode = 0x00020202,
> .prim_fifo_threshold = 0x0000c000,
> },
> .speedbins = ADRENO_SPEEDBINS(
> @@ -1202,6 +1215,7 @@ static const struct adreno_info a7xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a730_hwcg,
> .protect = &a730_protect,
> + .gmu_cgc_mode = 0x00020000,
> },
> .address_space_size = SZ_16G,
> }, {
> @@ -1221,6 +1235,7 @@ static const struct adreno_info a7xx_gpus[] = {
> .hwcg = a740_hwcg,
> .protect = &a730_protect,
> .gmu_chipid = 0x7020100,
> + .gmu_cgc_mode = 0x00020202,
> },
> .address_space_size = SZ_16G,
> }, {
> @@ -1239,6 +1254,7 @@ static const struct adreno_info a7xx_gpus[] = {
> .hwcg = a740_hwcg,
> .protect = &a730_protect,
> .gmu_chipid = 0x7050001,
> + .gmu_cgc_mode = 0x00020202,
> },
> .address_space_size = SZ_256G,
> }, {
> @@ -1257,6 +1273,7 @@ static const struct adreno_info a7xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .protect = &a730_protect,
> .gmu_chipid = 0x7090100,
> + .gmu_cgc_mode = 0x00020202,
> },
> .address_space_size = SZ_16G,
> }
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index aaeb1161f90d..871452daa189 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -402,7 +402,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
> const struct adreno_reglist *reg;
> unsigned int i;
> - u32 val, clock_cntl_on, cgc_mode;
> + u32 val, clock_cntl_on;
>
> if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu)))
> return;
> @@ -417,10 +417,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> clock_cntl_on = 0x8aa8aa82;
>
> if (adreno_is_a7xx(adreno_gpu)) {
> - cgc_mode = adreno_is_a740_family(adreno_gpu) ? 0x20222 : 0x20000;
> -
This does appear to change the gmu_cgc_mode in nearly all cases.. was
this intended?
BR,
-R
> gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
> - state ? cgc_mode : 0);
> + state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
> gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
> state ? 0x10111 : 0);
> gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> index bc37bd8c7f65..0fb7febf70e7 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> @@ -22,6 +22,7 @@ struct a6xx_info {
> const struct adreno_reglist *hwcg;
> const struct adreno_protect *protect;
> u32 gmu_chipid;
> + u32 gmu_cgc_mode;
> u32 prim_fifo_threshold;
> };
>
>
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/5] drm/msm/a6xx: Store gmu_cgc_mode in struct a6xx_info
2024-08-26 21:07 ` Rob Clark
@ 2024-08-26 21:09 ` Rob Clark
2024-08-27 20:12 ` Rob Clark
0 siblings, 1 reply; 11+ messages in thread
From: Rob Clark @ 2024-08-26 21:09 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Sean Paul, Abhinav Kumar, Dmitry Baryshkov, David Airlie,
Daniel Vetter, Marijn Suijten, linux-arm-msm, dri-devel,
freedreno, linux-kernel
On Mon, Aug 26, 2024 at 2:07 PM Rob Clark <robdclark@gmail.com> wrote:
>
> On Fri, Jul 19, 2024 at 3:03 AM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
> >
> > This was apparently almost never set on a6xx.. move the existing values
> > and fill out the remaining ones within the catalog.
> >
> > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> > ---
> > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 19 ++++++++++++++++++-
> > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++----
> > drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
> > 3 files changed, 21 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> > index 1ea535960f32..deee0b686962 100644
> > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> > @@ -448,7 +448,6 @@ static const struct adreno_reglist a690_hwcg[] = {
> > {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
> > {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
> > {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
> > - {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
> > {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
> > {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
> > {}
> > @@ -636,6 +635,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > .a6xx = &(const struct a6xx_info) {
> > .hwcg = a612_hwcg,
> > .protect = &a630_protect,
> > + .gmu_cgc_mode = 0x00020202,
> > .prim_fifo_threshold = 0x00080000,
> > },
> > /*
> > @@ -668,6 +668,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > .a6xx = &(const struct a6xx_info) {
> > .hwcg = a615_hwcg,
> > .protect = &a630_protect,
> > + .gmu_cgc_mode = 0x00000222,
> > .prim_fifo_threshold = 0x00180000,
> > },
> > .speedbins = ADRENO_SPEEDBINS(
> > @@ -691,6 +692,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > .init = a6xx_gpu_init,
> > .a6xx = &(const struct a6xx_info) {
> > .protect = &a630_protect,
> > + .gmu_cgc_mode = 0x00000222,
> > .prim_fifo_threshold = 0x00180000,
> > },
> > .speedbins = ADRENO_SPEEDBINS(
> > @@ -714,6 +716,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > .a6xx = &(const struct a6xx_info) {
> > .hwcg = a615_hwcg,
> > .protect = &a630_protect,
> > + .gmu_cgc_mode = 0x00000222,
> > .prim_fifo_threshold = 0x00018000,
> > },
> > .speedbins = ADRENO_SPEEDBINS(
> > @@ -737,6 +740,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > .a6xx = &(const struct a6xx_info) {
> > .hwcg = a615_hwcg,
> > .protect = &a630_protect,
> > + .gmu_cgc_mode = 0x00000222,
> > .prim_fifo_threshold = 0x00018000,
> > },
> > .speedbins = ADRENO_SPEEDBINS(
> > @@ -760,6 +764,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > .a6xx = &(const struct a6xx_info) {
> > .hwcg = a615_hwcg,
> > .protect = &a630_protect,
> > + .gmu_cgc_mode = 0x00000222,
> > .prim_fifo_threshold = 0x00018000,
> > },
> > .speedbins = ADRENO_SPEEDBINS(
> > @@ -788,6 +793,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > .a6xx = &(const struct a6xx_info) {
> > .hwcg = a630_hwcg,
> > .protect = &a630_protect,
> > + .gmu_cgc_mode = 0x00020202,
> > .prim_fifo_threshold = 0x00180000,
> > },
> > }, {
> > @@ -806,6 +812,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > .a6xx = &(const struct a6xx_info) {
> > .hwcg = a640_hwcg,
> > .protect = &a630_protect,
> > + .gmu_cgc_mode = 0x00020202,
> > .prim_fifo_threshold = 0x00180000,
> > },
> > .speedbins = ADRENO_SPEEDBINS(
> > @@ -829,6 +836,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > .a6xx = &(const struct a6xx_info) {
> > .hwcg = a650_hwcg,
> > .protect = &a650_protect,
> > + .gmu_cgc_mode = 0x00020202,
> > .prim_fifo_threshold = 0x00300200,
> > },
> > .address_space_size = SZ_16G,
> > @@ -855,6 +863,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > .a6xx = &(const struct a6xx_info) {
> > .hwcg = a660_hwcg,
> > .protect = &a660_protect,
> > + .gmu_cgc_mode = 0x00020000,
> > .prim_fifo_threshold = 0x00300200,
> > },
> > .address_space_size = SZ_16G,
> > @@ -874,6 +883,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > .a6xx = &(const struct a6xx_info) {
> > .hwcg = a660_hwcg,
> > .protect = &a660_protect,
> > + .gmu_cgc_mode = 0x00020202,
> > .prim_fifo_threshold = 0x00200200,
> > },
> > .address_space_size = SZ_16G,
> > @@ -899,6 +909,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > .a6xx = &(const struct a6xx_info) {
> > .hwcg = a640_hwcg,
> > .protect = &a630_protect,
> > + .gmu_cgc_mode = 0x00020202,
> > .prim_fifo_threshold = 0x00200200,
> > },
> > }, {
> > @@ -917,6 +928,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > .a6xx = &(const struct a6xx_info) {
> > .hwcg = a690_hwcg,
> > .protect = &a690_protect,
> > + .gmu_cgc_mode = 0x00020200,
> > .prim_fifo_threshold = 0x00800200,
> > },
> > .address_space_size = SZ_16G,
> > @@ -1178,6 +1190,7 @@ static const struct adreno_info a7xx_gpus[] = {
> > .a6xx = &(const struct a6xx_info) {
> > .hwcg = a702_hwcg,
> > .protect = &a650_protect,
> > + .gmu_cgc_mode = 0x00020202,
> > .prim_fifo_threshold = 0x0000c000,
> > },
> > .speedbins = ADRENO_SPEEDBINS(
> > @@ -1202,6 +1215,7 @@ static const struct adreno_info a7xx_gpus[] = {
> > .a6xx = &(const struct a6xx_info) {
> > .hwcg = a730_hwcg,
> > .protect = &a730_protect,
> > + .gmu_cgc_mode = 0x00020000,
> > },
> > .address_space_size = SZ_16G,
> > }, {
> > @@ -1221,6 +1235,7 @@ static const struct adreno_info a7xx_gpus[] = {
> > .hwcg = a740_hwcg,
> > .protect = &a730_protect,
> > .gmu_chipid = 0x7020100,
> > + .gmu_cgc_mode = 0x00020202,
> > },
> > .address_space_size = SZ_16G,
> > }, {
> > @@ -1239,6 +1254,7 @@ static const struct adreno_info a7xx_gpus[] = {
> > .hwcg = a740_hwcg,
> > .protect = &a730_protect,
> > .gmu_chipid = 0x7050001,
> > + .gmu_cgc_mode = 0x00020202,
> > },
> > .address_space_size = SZ_256G,
> > }, {
> > @@ -1257,6 +1273,7 @@ static const struct adreno_info a7xx_gpus[] = {
> > .a6xx = &(const struct a6xx_info) {
> > .protect = &a730_protect,
> > .gmu_chipid = 0x7090100,
> > + .gmu_cgc_mode = 0x00020202,
> > },
> > .address_space_size = SZ_16G,
> > }
> > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > index aaeb1161f90d..871452daa189 100644
> > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > @@ -402,7 +402,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> > struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
> > const struct adreno_reglist *reg;
> > unsigned int i;
> > - u32 val, clock_cntl_on, cgc_mode;
> > + u32 val, clock_cntl_on;
> >
> > if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu)))
> > return;
> > @@ -417,10 +417,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> > clock_cntl_on = 0x8aa8aa82;
> >
> > if (adreno_is_a7xx(adreno_gpu)) {
> > - cgc_mode = adreno_is_a740_family(adreno_gpu) ? 0x20222 : 0x20000;
> > -
>
> This does appear to change the gmu_cgc_mode in nearly all cases.. was
> this intended?
Hmm, and this will only get written for a7xx, so we're dropping the
reg write for a690..
> BR,
> -R
>
> > gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
> > - state ? cgc_mode : 0);
> > + state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
> > gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
> > state ? 0x10111 : 0);
> > gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,
> > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> > index bc37bd8c7f65..0fb7febf70e7 100644
> > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> > @@ -22,6 +22,7 @@ struct a6xx_info {
> > const struct adreno_reglist *hwcg;
> > const struct adreno_protect *protect;
> > u32 gmu_chipid;
> > + u32 gmu_cgc_mode;
> > u32 prim_fifo_threshold;
> > };
> >
> >
> > --
> > 2.45.2
> >
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/5] drm/msm/a6xx: Store gmu_cgc_mode in struct a6xx_info
2024-08-26 21:09 ` Rob Clark
@ 2024-08-27 20:12 ` Rob Clark
2024-08-28 11:16 ` Konrad Dybcio
0 siblings, 1 reply; 11+ messages in thread
From: Rob Clark @ 2024-08-27 20:12 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Sean Paul, Abhinav Kumar, Dmitry Baryshkov, David Airlie,
Daniel Vetter, Marijn Suijten, linux-arm-msm, dri-devel,
freedreno, linux-kernel, Konrad Dybcio
resending with updated Konrad email addr
On Mon, Aug 26, 2024 at 2:09 PM Rob Clark <robdclark@gmail.com> wrote:
>
> On Mon, Aug 26, 2024 at 2:07 PM Rob Clark <robdclark@gmail.com> wrote:
> >
> > On Fri, Jul 19, 2024 at 3:03 AM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
> > >
> > > This was apparently almost never set on a6xx.. move the existing values
> > > and fill out the remaining ones within the catalog.
> > >
> > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> > > ---
> > > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 19 ++++++++++++++++++-
> > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++----
> > > drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
> > > 3 files changed, 21 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> > > index 1ea535960f32..deee0b686962 100644
> > > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> > > @@ -448,7 +448,6 @@ static const struct adreno_reglist a690_hwcg[] = {
> > > {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
> > > {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
> > > {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
> > > - {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
> > > {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
> > > {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
> > > {}
> > > @@ -636,6 +635,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > > .a6xx = &(const struct a6xx_info) {
> > > .hwcg = a612_hwcg,
> > > .protect = &a630_protect,
> > > + .gmu_cgc_mode = 0x00020202,
> > > .prim_fifo_threshold = 0x00080000,
> > > },
> > > /*
> > > @@ -668,6 +668,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > > .a6xx = &(const struct a6xx_info) {
> > > .hwcg = a615_hwcg,
> > > .protect = &a630_protect,
> > > + .gmu_cgc_mode = 0x00000222,
> > > .prim_fifo_threshold = 0x00180000,
> > > },
> > > .speedbins = ADRENO_SPEEDBINS(
> > > @@ -691,6 +692,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > > .init = a6xx_gpu_init,
> > > .a6xx = &(const struct a6xx_info) {
> > > .protect = &a630_protect,
> > > + .gmu_cgc_mode = 0x00000222,
> > > .prim_fifo_threshold = 0x00180000,
> > > },
> > > .speedbins = ADRENO_SPEEDBINS(
> > > @@ -714,6 +716,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > > .a6xx = &(const struct a6xx_info) {
> > > .hwcg = a615_hwcg,
> > > .protect = &a630_protect,
> > > + .gmu_cgc_mode = 0x00000222,
> > > .prim_fifo_threshold = 0x00018000,
> > > },
> > > .speedbins = ADRENO_SPEEDBINS(
> > > @@ -737,6 +740,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > > .a6xx = &(const struct a6xx_info) {
> > > .hwcg = a615_hwcg,
> > > .protect = &a630_protect,
> > > + .gmu_cgc_mode = 0x00000222,
> > > .prim_fifo_threshold = 0x00018000,
> > > },
> > > .speedbins = ADRENO_SPEEDBINS(
> > > @@ -760,6 +764,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > > .a6xx = &(const struct a6xx_info) {
> > > .hwcg = a615_hwcg,
> > > .protect = &a630_protect,
> > > + .gmu_cgc_mode = 0x00000222,
> > > .prim_fifo_threshold = 0x00018000,
> > > },
> > > .speedbins = ADRENO_SPEEDBINS(
> > > @@ -788,6 +793,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > > .a6xx = &(const struct a6xx_info) {
> > > .hwcg = a630_hwcg,
> > > .protect = &a630_protect,
> > > + .gmu_cgc_mode = 0x00020202,
> > > .prim_fifo_threshold = 0x00180000,
> > > },
> > > }, {
> > > @@ -806,6 +812,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > > .a6xx = &(const struct a6xx_info) {
> > > .hwcg = a640_hwcg,
> > > .protect = &a630_protect,
> > > + .gmu_cgc_mode = 0x00020202,
> > > .prim_fifo_threshold = 0x00180000,
> > > },
> > > .speedbins = ADRENO_SPEEDBINS(
> > > @@ -829,6 +836,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > > .a6xx = &(const struct a6xx_info) {
> > > .hwcg = a650_hwcg,
> > > .protect = &a650_protect,
> > > + .gmu_cgc_mode = 0x00020202,
> > > .prim_fifo_threshold = 0x00300200,
> > > },
> > > .address_space_size = SZ_16G,
> > > @@ -855,6 +863,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > > .a6xx = &(const struct a6xx_info) {
> > > .hwcg = a660_hwcg,
> > > .protect = &a660_protect,
> > > + .gmu_cgc_mode = 0x00020000,
> > > .prim_fifo_threshold = 0x00300200,
> > > },
> > > .address_space_size = SZ_16G,
> > > @@ -874,6 +883,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > > .a6xx = &(const struct a6xx_info) {
> > > .hwcg = a660_hwcg,
> > > .protect = &a660_protect,
> > > + .gmu_cgc_mode = 0x00020202,
> > > .prim_fifo_threshold = 0x00200200,
> > > },
> > > .address_space_size = SZ_16G,
> > > @@ -899,6 +909,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > > .a6xx = &(const struct a6xx_info) {
> > > .hwcg = a640_hwcg,
> > > .protect = &a630_protect,
> > > + .gmu_cgc_mode = 0x00020202,
> > > .prim_fifo_threshold = 0x00200200,
> > > },
> > > }, {
> > > @@ -917,6 +928,7 @@ static const struct adreno_info a6xx_gpus[] = {
> > > .a6xx = &(const struct a6xx_info) {
> > > .hwcg = a690_hwcg,
> > > .protect = &a690_protect,
> > > + .gmu_cgc_mode = 0x00020200,
> > > .prim_fifo_threshold = 0x00800200,
> > > },
> > > .address_space_size = SZ_16G,
> > > @@ -1178,6 +1190,7 @@ static const struct adreno_info a7xx_gpus[] = {
> > > .a6xx = &(const struct a6xx_info) {
> > > .hwcg = a702_hwcg,
> > > .protect = &a650_protect,
> > > + .gmu_cgc_mode = 0x00020202,
> > > .prim_fifo_threshold = 0x0000c000,
> > > },
> > > .speedbins = ADRENO_SPEEDBINS(
> > > @@ -1202,6 +1215,7 @@ static const struct adreno_info a7xx_gpus[] = {
> > > .a6xx = &(const struct a6xx_info) {
> > > .hwcg = a730_hwcg,
> > > .protect = &a730_protect,
> > > + .gmu_cgc_mode = 0x00020000,
> > > },
> > > .address_space_size = SZ_16G,
> > > }, {
> > > @@ -1221,6 +1235,7 @@ static const struct adreno_info a7xx_gpus[] = {
> > > .hwcg = a740_hwcg,
> > > .protect = &a730_protect,
> > > .gmu_chipid = 0x7020100,
> > > + .gmu_cgc_mode = 0x00020202,
> > > },
> > > .address_space_size = SZ_16G,
> > > }, {
> > > @@ -1239,6 +1254,7 @@ static const struct adreno_info a7xx_gpus[] = {
> > > .hwcg = a740_hwcg,
> > > .protect = &a730_protect,
> > > .gmu_chipid = 0x7050001,
> > > + .gmu_cgc_mode = 0x00020202,
> > > },
> > > .address_space_size = SZ_256G,
> > > }, {
> > > @@ -1257,6 +1273,7 @@ static const struct adreno_info a7xx_gpus[] = {
> > > .a6xx = &(const struct a6xx_info) {
> > > .protect = &a730_protect,
> > > .gmu_chipid = 0x7090100,
> > > + .gmu_cgc_mode = 0x00020202,
> > > },
> > > .address_space_size = SZ_16G,
> > > }
> > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > index aaeb1161f90d..871452daa189 100644
> > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > @@ -402,7 +402,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> > > struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
> > > const struct adreno_reglist *reg;
> > > unsigned int i;
> > > - u32 val, clock_cntl_on, cgc_mode;
> > > + u32 val, clock_cntl_on;
> > >
> > > if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu)))
> > > return;
> > > @@ -417,10 +417,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> > > clock_cntl_on = 0x8aa8aa82;
> > >
> > > if (adreno_is_a7xx(adreno_gpu)) {
> > > - cgc_mode = adreno_is_a740_family(adreno_gpu) ? 0x20222 : 0x20000;
> > > -
> >
> > This does appear to change the gmu_cgc_mode in nearly all cases.. was
> > this intended?
>
> Hmm, and this will only get written for a7xx, so we're dropping the
> reg write for a690..
>
> > BR,
> > -R
> >
> > > gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
> > > - state ? cgc_mode : 0);
> > > + state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
> > > gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
> > > state ? 0x10111 : 0);
> > > gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,
> > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> > > index bc37bd8c7f65..0fb7febf70e7 100644
> > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> > > @@ -22,6 +22,7 @@ struct a6xx_info {
> > > const struct adreno_reglist *hwcg;
> > > const struct adreno_protect *protect;
> > > u32 gmu_chipid;
> > > + u32 gmu_cgc_mode;
> > > u32 prim_fifo_threshold;
> > > };
> > >
> > >
> > > --
> > > 2.45.2
> > >
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/5] drm/msm/a6xx: Store gmu_cgc_mode in struct a6xx_info
2024-08-27 20:12 ` Rob Clark
@ 2024-08-28 11:16 ` Konrad Dybcio
2024-08-28 13:44 ` Rob Clark
0 siblings, 1 reply; 11+ messages in thread
From: Konrad Dybcio @ 2024-08-28 11:16 UTC (permalink / raw)
To: Rob Clark, Konrad Dybcio
Cc: Sean Paul, Abhinav Kumar, Dmitry Baryshkov, David Airlie,
Daniel Vetter, Marijn Suijten, linux-arm-msm, dri-devel,
freedreno, linux-kernel, Konrad Dybcio
On 27.08.2024 10:12 PM, Rob Clark wrote:
> resending with updated Konrad email addr
>
> On Mon, Aug 26, 2024 at 2:09 PM Rob Clark <robdclark@gmail.com> wrote:
>>
>> On Mon, Aug 26, 2024 at 2:07 PM Rob Clark <robdclark@gmail.com> wrote:
>>>
>>> On Fri, Jul 19, 2024 at 3:03 AM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>>>
>>>> This was apparently almost never set on a6xx.. move the existing values
>>>> and fill out the remaining ones within the catalog.
>>>>
>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>>> ---
[...]
>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>>> @@ -402,7 +402,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
>>>> struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
>>>> const struct adreno_reglist *reg;
>>>> unsigned int i;
>>>> - u32 val, clock_cntl_on, cgc_mode;
>>>> + u32 val, clock_cntl_on;
>>>>
>>>> if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu)))
>>>> return;
>>>> @@ -417,10 +417,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
>>>> clock_cntl_on = 0x8aa8aa82;
>>>>
>>>> if (adreno_is_a7xx(adreno_gpu)) {
>>>> - cgc_mode = adreno_is_a740_family(adreno_gpu) ? 0x20222 : 0x20000;
>>>> -
>>>
>>> This does appear to change the gmu_cgc_mode in nearly all cases.. was
>>> this intended?
>>
>> Hmm, and this will only get written for a7xx, so we're dropping the
>> reg write for a690..
Right, this patch is a lot to chew through.. It:
- adds the proper magic value per gpu gen
- removes the sneaky a690 write
- uses the new struct entry
but also
- fails to remove the if (a7xx) check
so I suppose for v2 I can split it into:
1. add the magic values
2. fix the if (a7xx) check
3. use the struct value and drop the a690 one
does that sound good?
Konrad
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/5] drm/msm/a6xx: Store gmu_cgc_mode in struct a6xx_info
2024-08-28 11:16 ` Konrad Dybcio
@ 2024-08-28 13:44 ` Rob Clark
0 siblings, 0 replies; 11+ messages in thread
From: Rob Clark @ 2024-08-28 13:44 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Sean Paul, Abhinav Kumar, Dmitry Baryshkov, David Airlie,
Daniel Vetter, Marijn Suijten, linux-arm-msm, dri-devel,
freedreno, linux-kernel, Konrad Dybcio
On Wed, Aug 28, 2024 at 4:16 AM Konrad Dybcio <konradybcio@kernel.org> wrote:
>
> On 27.08.2024 10:12 PM, Rob Clark wrote:
> > resending with updated Konrad email addr
> >
> > On Mon, Aug 26, 2024 at 2:09 PM Rob Clark <robdclark@gmail.com> wrote:
> >>
> >> On Mon, Aug 26, 2024 at 2:07 PM Rob Clark <robdclark@gmail.com> wrote:
> >>>
> >>> On Fri, Jul 19, 2024 at 3:03 AM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
> >>>>
> >>>> This was apparently almost never set on a6xx.. move the existing values
> >>>> and fill out the remaining ones within the catalog.
> >>>>
> >>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> >>>> ---
>
> [...]
>
> >>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >>>> @@ -402,7 +402,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> >>>> struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
> >>>> const struct adreno_reglist *reg;
> >>>> unsigned int i;
> >>>> - u32 val, clock_cntl_on, cgc_mode;
> >>>> + u32 val, clock_cntl_on;
> >>>>
> >>>> if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu)))
> >>>> return;
> >>>> @@ -417,10 +417,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> >>>> clock_cntl_on = 0x8aa8aa82;
> >>>>
> >>>> if (adreno_is_a7xx(adreno_gpu)) {
> >>>> - cgc_mode = adreno_is_a740_family(adreno_gpu) ? 0x20222 : 0x20000;
> >>>> -
> >>>
> >>> This does appear to change the gmu_cgc_mode in nearly all cases.. was
> >>> this intended?
> >>
> >> Hmm, and this will only get written for a7xx, so we're dropping the
> >> reg write for a690..
>
> Right, this patch is a lot to chew through.. It:
>
> - adds the proper magic value per gpu gen
> - removes the sneaky a690 write
> - uses the new struct entry
>
> but also
>
> - fails to remove the if (a7xx) check
>
> so I suppose for v2 I can split it into:
>
> 1. add the magic values
> 2. fix the if (a7xx) check
> 3. use the struct value and drop the a690 one
>
> does that sound good?
Yeah, I would prefer if it were split up to make it clear that the
magic value changes were intentional
ps. there is a _bit_ more time to get this in to msm-next for v6.12,
but not much
BR,
-R
> Konrad
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2024-08-28 13:44 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-07-19 10:03 [PATCH 0/5] A621 support Konrad Dybcio
2024-07-19 10:03 ` [PATCH 1/5] drm/msm/a6xx: Evaluate adreno_is_a650_family in pdc_in_aop check Konrad Dybcio
2024-07-19 10:03 ` [PATCH 2/5] drm/msm/a6xx: Store primFifoThreshold in struct a6xx_info Konrad Dybcio
2024-07-19 10:03 ` [PATCH 3/5] drm/msm/a6xx: Store gmu_cgc_mode " Konrad Dybcio
2024-08-26 21:07 ` Rob Clark
2024-08-26 21:09 ` Rob Clark
2024-08-27 20:12 ` Rob Clark
2024-08-28 11:16 ` Konrad Dybcio
2024-08-28 13:44 ` Rob Clark
2024-07-19 10:03 ` [PATCH 4/5] drm/msm/a6xx: Set GMU CGC properties on a6xx too Konrad Dybcio
2024-07-19 10:03 ` [PATCH 5/5] drm/msm/a6xx: Add A621 support Konrad Dybcio
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®