Re: [PATCH] EDAC/altera: Handle OCRAM ECC enable after warm reset

[Dinh Nguyen <dinguyen@kernel.org>]

On 11/3/25 08:09, niravkumarlaxmidas.rabara@altera.com wrote:
> From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
> 
> The OCRAM ECC is always enabled either by the BootROM or by the Secure
> Device Manager (SDM) during a power-on reset on SoCFPGA.
> 
> However, during a warm reset, the OCRAM content is retained to preserve
> data, while the control and status registers are reset to their default
> values. As a result, ECC must be explicitly re-enabled after a warm reset.
> 
> Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
> ---
>   drivers/edac/altera_edac.c | 18 +++++++++++++++---
>   1 file changed, 15 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
> index 103b2c2eba2a..a776d61027f2 100644
> --- a/drivers/edac/altera_edac.c
> +++ b/drivers/edac/altera_edac.c
> @@ -1184,10 +1184,22 @@ altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
>   	if (ret)
>   		return ret;
>   
> -	/* Verify OCRAM has been initialized */
> +	/*
> +	 * Verify that OCRAM has been initialized.
> +	 * During a warm reset, OCRAM contents are retained, but the control
> +	 * and status registers are reset to their default values. Therefore,
> +	 * ECC must be explicitly re-enabled in the control register.
> +	 * Error condition: if INITCOMPLETEA is clear and ECC_EN is already set.
> +	 */
>   	if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
> -			   (base + ALTR_A10_ECC_INITSTAT_OFST)))
> -		return -ENODEV;
> +			   (base + ALTR_A10_ECC_INITSTAT_OFST))) {
> +		if (!ecc_test_bits(ALTR_A10_ECC_EN,
> +				   (base + ALTR_A10_ECC_CTRL_OFST)))
> +			ecc_set_bits(ALTR_A10_ECC_EN,
> +				     (base + ALTR_A10_ECC_CTRL_OFST));
> +		else
> +			return -ENODEV;
> +	}
>   
>   	/* Enable IRQ on Single Bit Error */
>   	writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));


Acked-by: Dinh Nguyen <dinguyen@kernel.org>