* [PATCH v2] arm64: dts: qcom: shikra: Switch CPU ETMs to MMIO-based probing
@ 2026-10-19 6:58 Jie Gan
2026-10-19 9:10 ` Konrad Dybcio
2026-10-19 10:25 ` Abel Vesa
0 siblings, 2 replies; 3+ messages in thread
From: Jie Gan @ 2026-10-19 6:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jie Gan
Cc: Konrad Dybcio, linux-arm-msm, devicetree, linux-kernel
The etm0-etm3 nodes are declared with "arm,coresight-etm4x-sysreg"
but do not implement self-hosted system-register trace access on
this SoC: ID_AA64DFR0_EL1.TraceVer reads as 0 on the affected CPUs,
so etm4_init_sysreg_access() correctly reports the access mechanism
as unavailable and the ETMv4 driver fails to probe with -EINVAL.
The CPU ETMs have a memory-mapped aperture, so switch each node to
the standard "arm,coresight-etm4x", "arm,primecell" compatible with
its MMIO reg range.
Fixes: eed738c6dd0c ("arm64: dts: qcom: shikra: Add coresight nodes")
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
Changes in v2:
- add arm,coresight-loses-context-with-cpu property for ETM nodes.
- Link to v1: https://lore.kernel.org/r/20260922-fix-etm-probe-issue-on-shikra-v1-1-56d25e9bbe17@oss.qualcomm.com
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 144 ++++++++++++++++++-----------------
1 file changed, 76 insertions(+), 68 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 2623e139196f..2ddbd61567d8 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -166,74 +166,6 @@ eud_in: endpoint {
};
};
- etm0 {
- compatible = "arm,coresight-etm4x-sysreg";
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
- clock-names = "apb_pclk";
- cpu = <&cpu0>;
- qcom,skip-power-up;
-
- out-ports {
- port {
- etm0_out: endpoint {
- remote-endpoint = <&funnel_cpuss0_in0>;
- };
- };
- };
- };
-
- etm1 {
- compatible = "arm,coresight-etm4x-sysreg";
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
- clock-names = "apb_pclk";
- cpu = <&cpu1>;
- qcom,skip-power-up;
-
- out-ports {
- port {
- etm1_out: endpoint {
- remote-endpoint = <&funnel_cpuss0_in1>;
- };
- };
- };
- };
-
- etm2 {
- compatible = "arm,coresight-etm4x-sysreg";
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
- clock-names = "apb_pclk";
- cpu = <&cpu2>;
- qcom,skip-power-up;
-
- out-ports {
- port {
- etm2_out: endpoint {
- remote-endpoint = <&funnel_cpuss0_in2>;
- };
- };
- };
- };
-
- etm3 {
- compatible = "arm,coresight-etm4x-sysreg";
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
- clock-names = "apb_pclk";
- cpu = <&cpu3>;
- qcom,skip-power-up;
-
- out-ports {
- port {
- etm3_out: endpoint {
- remote-endpoint = <&funnel_cpuss0_in3>;
- };
- };
- };
- };
-
firmware {
scm {
compatible = "qcom,scm-shikra", "qcom,scm";
@@ -3740,6 +3672,25 @@ cti@9020000 {
label = "cti_apss_pe0";
};
+ etm@9040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x0 0x09040000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint = <&funnel_cpuss0_in0>;
+ };
+ };
+ };
+ };
+
cti@90e0000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x090e0000 0x0 0x1000>;
@@ -3758,6 +3709,25 @@ cti@9120000 {
label = "cti_apss_pe1";
};
+ etm@9140000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x0 0x09140000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu1>;
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint = <&funnel_cpuss0_in1>;
+ };
+ };
+ };
+ };
+
cti@9220000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x09220000 0x0 0x1000>;
@@ -3767,6 +3737,25 @@ cti@9220000 {
label = "cti_apss_pe2";
};
+ etm@9240000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x0 0x09240000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu2>;
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint = <&funnel_cpuss0_in2>;
+ };
+ };
+ };
+ };
+
cti@9320000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x09320000 0x0 0x1000>;
@@ -3776,6 +3765,25 @@ cti@9320000 {
label = "cti_apss_pe3";
};
+ etm@9340000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x0 0x09340000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu3>;
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint = <&funnel_cpuss0_in3>;
+ };
+ };
+ };
+ };
+
funnel@9800000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x09800000 0x0 0x1000>;
---
base-commit: 2efb7a11f1aa4d2dc285fe2680cca22cb9f72f64
change-id: 20260922-fix-etm-probe-issue-on-shikra-5a624f583975
Best regards,
--
Jie Gan <jie.gan@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] arm64: dts: qcom: shikra: Switch CPU ETMs to MMIO-based probing
2026-10-19 6:58 [PATCH v2] arm64: dts: qcom: shikra: Switch CPU ETMs to MMIO-based probing Jie Gan
@ 2026-10-19 9:10 ` Konrad Dybcio
2026-10-19 10:25 ` Abel Vesa
1 sibling, 0 replies; 3+ messages in thread
From: Konrad Dybcio @ 2026-10-19 9:10 UTC (permalink / raw)
To: Jie Gan, Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/19/26 8:58 AM, Jie Gan wrote:
> The etm0-etm3 nodes are declared with "arm,coresight-etm4x-sysreg"
> but do not implement self-hosted system-register trace access on
> this SoC: ID_AA64DFR0_EL1.TraceVer reads as 0 on the affected CPUs,
> so etm4_init_sysreg_access() correctly reports the access mechanism
> as unavailable and the ETMv4 driver fails to probe with -EINVAL.
>
> The CPU ETMs have a memory-mapped aperture, so switch each node to
> the standard "arm,coresight-etm4x", "arm,primecell" compatible with
> its MMIO reg range.
>
> Fixes: eed738c6dd0c ("arm64: dts: qcom: shikra: Add coresight nodes")
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] arm64: dts: qcom: shikra: Switch CPU ETMs to MMIO-based probing
2026-10-19 6:58 [PATCH v2] arm64: dts: qcom: shikra: Switch CPU ETMs to MMIO-based probing Jie Gan
2026-10-19 9:10 ` Konrad Dybcio
@ 2026-10-19 10:25 ` Abel Vesa
1 sibling, 0 replies; 3+ messages in thread
From: Abel Vesa @ 2026-10-19 10:25 UTC (permalink / raw)
To: Jie Gan
Cc: Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, linux-arm-msm,
devicetree, linux-kernel
On 26-10-19 14:58:34, Jie Gan wrote:
> The etm0-etm3 nodes are declared with "arm,coresight-etm4x-sysreg"
> but do not implement self-hosted system-register trace access on
> this SoC: ID_AA64DFR0_EL1.TraceVer reads as 0 on the affected CPUs,
> so etm4_init_sysreg_access() correctly reports the access mechanism
> as unavailable and the ETMv4 driver fails to probe with -EINVAL.
>
> The CPU ETMs have a memory-mapped aperture, so switch each node to
> the standard "arm,coresight-etm4x", "arm,primecell" compatible with
> its MMIO reg range.
>
> Fixes: eed738c6dd0c ("arm64: dts: qcom: shikra: Add coresight nodes")
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2026-10-19 6:58 [PATCH v2] arm64: dts: qcom: shikra: Switch CPU ETMs to MMIO-based probing Jie Gan
2026-10-19 9:10 ` Konrad Dybcio
2026-10-19 10:25 ` Abel Vesa
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