From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: <nm@ti.com>, <vigneshr@ti.com>, <kristo@kernel.org>,
<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<francesco@dolcini.it>
Cc: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <danishanwar@ti.com>,
<srk@ti.com>, <s-vadapalli@ti.com>
Subject: Re: [PATCH v3 0/3] Add PCIe DT support for TI's J784S4 SoC
Date: Tue, 28 May 2024 14:26:13 +0530 [thread overview]
Message-ID: <3fd10101-1078-4979-b2d4-c5d4d7a40f4c@ti.com> (raw)
In-Reply-To: <20240523111008.4057988-1-s-vadapalli@ti.com>
On Thu, May 23, 2024 at 04:40:05PM +0530, Siddharth Vadapalli wrote:
> TI's J784S4 has two x4 Lane and two x2 Lane Gen3 PCIe Controllers.
> This series adds the device-tree nodes for all 4 PCIe instances in the
> SoC file. The Board (J784S4-EVM) has only PCIe0 and PCIe1 instances of
> PCIe brought out, due to which only those PCIe instances are being
> enabled in the board file. The device-tree overlay to enable PCIe0 and
> PCIe1 in Endpoint mode of operation is also included in this series.
Kindly ignore this series. I will post the v4 series with PCIe2 and
PCIe3 regions reserved in k3-j784s4.dtsi which I have missed in this
series.
Regards,
Siddharth.
prev parent reply other threads:[~2024-05-28 8:56 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-23 11:10 Siddharth Vadapalli
2024-05-23 11:10 ` [PATCH v3 1/3] arm64: dts: ti: k3-j784s4-main: Add PCIe nodes Siddharth Vadapalli
2024-05-23 11:10 ` [PATCH v3 2/3] arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode Siddharth Vadapalli
2024-05-23 11:10 ` [PATCH v3 3/3] arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIe0 and PCIe1 EP Mode Siddharth Vadapalli
2024-05-28 8:56 ` Siddharth Vadapalli [this message]
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