* [PATCH v3 0/3] Add PCIe DT support for TI's J784S4 SoC
@ 2024-05-23 11:10 Siddharth Vadapalli
2024-05-23 11:10 ` [PATCH v3 1/3] arm64: dts: ti: k3-j784s4-main: Add PCIe nodes Siddharth Vadapalli
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Siddharth Vadapalli @ 2024-05-23 11:10 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, francesco
Cc: devicetree, linux-kernel, linux-arm-kernel, danishanwar, srk,
s-vadapalli
TI's J784S4 has two x4 Lane and two x2 Lane Gen3 PCIe Controllers.
This series adds the device-tree nodes for all 4 PCIe instances in the
SoC file. The Board (J784S4-EVM) has only PCIe0 and PCIe1 instances of
PCIe brought out, due to which only those PCIe instances are being
enabled in the board file. The device-tree overlay to enable PCIe0 and
PCIe1 in Endpoint mode of operation is also included in this series.
v2:
https://lore.kernel.org/r/20240520101149.3243151-1-s-vadapalli@ti.com/
Changes since v2:
- Rebased on linux-next tagged next-20240523.
- Based on feedback from Francesco Dolcini <francesco@dolcini.it> at:
https://lore.kernel.org/r/20240521200909.GA3707@francesco-nb/
the device-tree nodes for PCIe2 and PCIe3 instances of PCIe have been
added.
v1:
https://lore.kernel.org/r/20240129114749.1197579-1-s-vadapalli@ti.com
Changes since v1:
- Rebased series on linux-next tagged next-20240520.
- All dependencies mentioned in v1 series have been met. This series has
no further dependencies for functionality.
- Added "pcie0_ctrl" and "pcie1_ctrl" nodes within the System Controller
node (scm_conf). This enables reusing the existing
"ti,syscon-pcie-ctrl" property without having to map the entire System
Controller region for configuring the PCIe specific registers within
"scm_conf". This change is also done in the "overlay" file in patch
3/3 w.r.t. providing the phandle to the pcie0_ctrl and pcie1_ctrl
nodes to the "ti,syscon-pcie-ctrl" property in the overlay.
Logs:
https://gist.github.com/Siddharth-Vadapalli-at-TI/cbf5255b72d7805e86331150a8b2b5c5
Regards,
Siddharth.
Siddharth Vadapalli (3):
arm64: dts: ti: k3-j784s4-main: Add PCIe nodes
arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode
arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIe0 and PCIe1 EP Mode
arch/arm64/boot/dts/ti/Makefile | 7 +-
.../dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso | 79 ++++++++++
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 46 ++++++
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 136 ++++++++++++++++++
4 files changed, 267 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso
--
2.40.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 1/3] arm64: dts: ti: k3-j784s4-main: Add PCIe nodes
2024-05-23 11:10 [PATCH v3 0/3] Add PCIe DT support for TI's J784S4 SoC Siddharth Vadapalli
@ 2024-05-23 11:10 ` Siddharth Vadapalli
2024-05-23 11:10 ` [PATCH v3 2/3] arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode Siddharth Vadapalli
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Siddharth Vadapalli @ 2024-05-23 11:10 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, francesco
Cc: devicetree, linux-kernel, linux-arm-kernel, danishanwar, srk,
s-vadapalli
TI's J784S4 SoC has four instances of Gen3 PCIe Controllers namely
PCIe0, PCIe1, PCIe2 and PCIe3. PCIe0 and PCIe1 are 4-Lane controllers
while PCIe2 and PCIe3 are 2-Lane controllers.
Add support for the Root Complex Mode of operation of these PCIe instances.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 136 +++++++++++++++++++++
1 file changed, 136 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 6a4554c6c9c1..7f89f8dc24df 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -48,6 +48,26 @@ scm_conf: bus@100000 {
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x1c000>;
+ pcie0_ctrl: pcie0-ctrl@4070 {
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ reg = <0x4070 0x4>;
+ };
+
+ pcie1_ctrl: pcie1-ctrl@4074 {
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ reg = <0x4074 0x4>;
+ };
+
+ pcie2_ctrl: pcie2-ctrl@4078 {
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ reg = <0x4078 0x4>;
+ };
+
+ pcie3_ctrl: pcie3-ctrl@407c {
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ reg = <0x407c 0x4>;
+ };
+
serdes_ln_ctrl: mux-controller@4080 {
compatible = "reg-mux";
reg = <0x00004080 0x30>;
@@ -907,6 +927,122 @@ main_sdhci1: mmc@4fb0000 {
status = "disabled";
};
+ pcie0_rc: pcie@2900000 {
+ compatible = "ti,j784s4-pcie-host";
+ reg = <0x00 0x02900000 0x00 0x1000>,
+ <0x00 0x02907000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x10000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 332 0>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb012>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
+ };
+
+ pcie1_rc: pcie@2910000 {
+ compatible = "ti,j784s4-pcie-host";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 333 0>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb012>;
+ msi-map = <0x0 &gic_its 0x10000 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
+ };
+
+ pcie2_rc: pcie@2920000 {
+ compatible = "ti,j784s4-pcie-host";
+ reg = <0x00 0x02920000 0x00 0x1000>,
+ <0x00 0x02927000 0x00 0x400>,
+ <0x00 0x0e000000 0x00 0x00800000>,
+ <0x44 0x00000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>;
+ max-link-speed = <3>;
+ num-lanes = <2>;
+ power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 334 0>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb012>;
+ msi-map = <0x0 &gic_its 0x20000 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
+ };
+
+ pcie3_rc: pcie@2930000 {
+ compatible = "ti,j784s4-pcie-host";
+ reg = <0x00 0x02930000 0x00 0x1000>,
+ <0x00 0x02937000 0x00 0x400>,
+ <0x00 0x0e800000 0x00 0x00800000>,
+ <0x44 0x10000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>;
+ max-link-speed = <3>;
+ num-lanes = <2>;
+ power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 335 0>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb012>;
+ msi-map = <0x0 &gic_its 0x30000 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
+ };
+
serdes_wiz0: wiz@5060000 {
compatible = "ti,j784s4-wiz-10g";
#address-cells = <1>;
--
2.40.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 2/3] arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode
2024-05-23 11:10 [PATCH v3 0/3] Add PCIe DT support for TI's J784S4 SoC Siddharth Vadapalli
2024-05-23 11:10 ` [PATCH v3 1/3] arm64: dts: ti: k3-j784s4-main: Add PCIe nodes Siddharth Vadapalli
@ 2024-05-23 11:10 ` Siddharth Vadapalli
2024-05-23 11:10 ` [PATCH v3 3/3] arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIe0 and PCIe1 EP Mode Siddharth Vadapalli
2024-05-28 8:56 ` [PATCH v3 0/3] Add PCIe DT support for TI's J784S4 SoC Siddharth Vadapalli
3 siblings, 0 replies; 5+ messages in thread
From: Siddharth Vadapalli @ 2024-05-23 11:10 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, francesco
Cc: devicetree, linux-kernel, linux-arm-kernel, danishanwar, srk,
s-vadapalli
Enable PCIe0 and PCIe1 instances of PCIe in Root Complex mode of
operation on J784S4 EVM. The lanes of PCIe0 are connected to Serdes1
instance of Serdes while the lanes of PCIe1 are connected to Serdes0
instance of Serdes in J784S4 SoC. Despite both PCIe instances supporting
up to 4 Lanes, since the physical connections to the PCIe connector
corresponding to the PCIe1 instance of PCIe are limited to 2 Lanes on
the J784S4 EVM, update the "num-lanes" property of PCIe1 accordingly.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 46 ++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index d511b25d62e3..31e88a6445f4 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -1105,3 +1105,49 @@ dp0_out: endpoint {
};
};
};
+
+&serdes0 {
+ status = "okay";
+ serdes0_pcie1_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <4>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>,
+ <&serdes_wiz0 3>, <&serdes_wiz0 4>;
+ };
+};
+
+&serdes_wiz0 {
+ status = "okay";
+};
+
+&pcie1_rc {
+ status = "okay";
+ num-lanes = <2>;
+ reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie1_link>;
+ phy-names = "pcie-phy";
+};
+
+&serdes1 {
+ status = "okay";
+ serdes1_pcie0_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+ };
+};
+
+&serdes_wiz1 {
+ status = "okay";
+};
+
+&pcie0_rc {
+ status = "okay";
+ reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes1_pcie0_link>;
+ phy-names = "pcie-phy";
+};
--
2.40.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 3/3] arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIe0 and PCIe1 EP Mode
2024-05-23 11:10 [PATCH v3 0/3] Add PCIe DT support for TI's J784S4 SoC Siddharth Vadapalli
2024-05-23 11:10 ` [PATCH v3 1/3] arm64: dts: ti: k3-j784s4-main: Add PCIe nodes Siddharth Vadapalli
2024-05-23 11:10 ` [PATCH v3 2/3] arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode Siddharth Vadapalli
@ 2024-05-23 11:10 ` Siddharth Vadapalli
2024-05-28 8:56 ` [PATCH v3 0/3] Add PCIe DT support for TI's J784S4 SoC Siddharth Vadapalli
3 siblings, 0 replies; 5+ messages in thread
From: Siddharth Vadapalli @ 2024-05-23 11:10 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, francesco
Cc: devicetree, linux-kernel, linux-arm-kernel, danishanwar, srk,
s-vadapalli
Add overlay to enable the PCIe0 and PCIe1 instances of PCIe on J784S4-EVM
in Endpoint mode of operation.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
arch/arm64/boot/dts/ti/Makefile | 7 +-
.../dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso | 79 +++++++++++++++++++
2 files changed, 85 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 2c327cc320cf..8673685e7528 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
# Boards with J784s4 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-pcie0-pcie1-ep.dtbo
# Build time test only, enabled by CONFIG_OF_ALL_DTBS
k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \
@@ -148,6 +149,8 @@ k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
k3-j721s2-evm-pcie1-ep.dtbo
+k3-j784s4-evm-pcie0-pcie1-ep-dtbs := k3-j784s4-evm.dtb \
+ k3-j784s4-evm-pcie0-pcie1-ep.dtbo
dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-am625-beagleplay-csi2-tevi-ov5640.dtb \
k3-am625-sk-csi2-imx219.dtb \
@@ -168,7 +171,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-am69-sk-csi2-dual-imx219.dtb \
k3-j721e-evm-pcie0-ep.dtb \
k3-j721e-sk-csi2-dual-imx219.dtb \
- k3-j721s2-evm-pcie1-ep.dtb
+ k3-j721s2-evm-pcie1-ep.dtb \
+ k3-j784s4-evm-pcie0-pcie1-ep.dtb
# Enable support for device-tree overlays
DTC_FLAGS_k3-am625-beagleplay += -@
@@ -186,3 +190,4 @@ DTC_FLAGS_k3-am69-sk += -@
DTC_FLAGS_k3-j721e-common-proc-board += -@
DTC_FLAGS_k3-j721e-sk += -@
DTC_FLAGS_k3-j721s2-common-proc-board += -@
+DTC_FLAGS_k3-j784s4-evm += -@
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso
new file mode 100644
index 000000000000..685305092bd8
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT Overlay for enabling PCIE0 and PCIE1 instances in Endpoint Configuration
+ * on J784S4 EVM.
+ *
+ * J784S4 EVM Product Link: https://www.ti.com/tool/J784S4XEVM
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+#include "k3-pinctrl.h"
+
+/*
+ * Since Root Complex and Endpoint modes are mutually exclusive
+ * disable Root Complex mode.
+ */
+&pcie0_rc {
+ status = "disabled";
+};
+
+&pcie1_rc {
+ status = "disabled";
+};
+
+&cbass_main {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic500>;
+
+ pcie0_ep: pcie-ep@2900000 {
+ compatible = "ti,j784s4-pcie-ep";
+ reg = <0x00 0x02900000 0x00 0x1000>,
+ <0x00 0x02907000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x10000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 332 0>;
+ clock-names = "fck";
+ max-functions = /bits/ 8 <6>;
+ max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+ dma-coherent;
+ phys = <&serdes1_pcie0_link>;
+ phy-names = "pcie-phy";
+ };
+
+ pcie1_ep: pcie-ep@2910000 {
+ compatible = "ti,j784s4-pcie-ep";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
+ max-link-speed = <3>;
+ num-lanes = <2>;
+ power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 333 0>;
+ clock-names = "fck";
+ max-functions = /bits/ 8 <6>;
+ max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+ dma-coherent;
+ phys = <&serdes0_pcie1_link>;
+ phy-names = "pcie-phy";
+ };
+};
--
2.40.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3 0/3] Add PCIe DT support for TI's J784S4 SoC
2024-05-23 11:10 [PATCH v3 0/3] Add PCIe DT support for TI's J784S4 SoC Siddharth Vadapalli
` (2 preceding siblings ...)
2024-05-23 11:10 ` [PATCH v3 3/3] arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIe0 and PCIe1 EP Mode Siddharth Vadapalli
@ 2024-05-28 8:56 ` Siddharth Vadapalli
3 siblings, 0 replies; 5+ messages in thread
From: Siddharth Vadapalli @ 2024-05-28 8:56 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, francesco
Cc: devicetree, linux-kernel, linux-arm-kernel, danishanwar, srk,
s-vadapalli
On Thu, May 23, 2024 at 04:40:05PM +0530, Siddharth Vadapalli wrote:
> TI's J784S4 has two x4 Lane and two x2 Lane Gen3 PCIe Controllers.
> This series adds the device-tree nodes for all 4 PCIe instances in the
> SoC file. The Board (J784S4-EVM) has only PCIe0 and PCIe1 instances of
> PCIe brought out, due to which only those PCIe instances are being
> enabled in the board file. The device-tree overlay to enable PCIe0 and
> PCIe1 in Endpoint mode of operation is also included in this series.
Kindly ignore this series. I will post the v4 series with PCIe2 and
PCIe3 regions reserved in k3-j784s4.dtsi which I have missed in this
series.
Regards,
Siddharth.
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2024-05-23 11:10 [PATCH v3 0/3] Add PCIe DT support for TI's J784S4 SoC Siddharth Vadapalli
2024-05-23 11:10 ` [PATCH v3 1/3] arm64: dts: ti: k3-j784s4-main: Add PCIe nodes Siddharth Vadapalli
2024-05-23 11:10 ` [PATCH v3 2/3] arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode Siddharth Vadapalli
2024-05-23 11:10 ` [PATCH v3 3/3] arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIe0 and PCIe1 EP Mode Siddharth Vadapalli
2024-05-28 8:56 ` [PATCH v3 0/3] Add PCIe DT support for TI's J784S4 SoC Siddharth Vadapalli
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