From: Margit Schubert-While <margit@margit.com>
To: linux-kernel@vger.kernel.org
Subject: L1_CACHE_SHIFT value for P4 ?
Date: Thu, 21 Nov 2002 14:25:54 +0100 [thread overview]
Message-ID: <4.3.2.7.2.20021121142223.00b546c0@mail.dns-host.com> (raw)
Andi,
L2 cache lines = L2 cache size ?
This P4 has got 512KB L2 cache.
processor : 0
vendor_id : GenuineIntel
cpu family : 15
model : 2
model name : Intel(R) Pentium(R) 4 CPU 2.40GHz
stepping : 4
cpu MHz : 2400.143
cache size : 512 KB
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 2
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr
pge mca cmov pat pse36
clflush dts acpi mmx fxsr sse sse2 ss ht tm
bogomips : 4784.12
next reply other threads:[~2002-11-21 13:18 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-11-21 13:25 Margit Schubert-While [this message]
2002-11-21 13:30 ` Dave Jones
-- strict thread matches above, loose matches on Subject: below --
2002-11-21 14:39 Margit Schubert-While
[not found] <4.3.2.7.2.20021121130236.00b15370@mail.dns-host.com.suse.lists.linux.kernel>
2002-11-21 13:10 ` Andi Kleen
2002-11-21 13:23 ` Dave Jones
2002-11-21 13:42 ` Andi Kleen
2002-11-21 13:47 ` Dave Jones
2002-11-21 15:03 ` Mikael Pettersson
2002-11-21 12:13 Margit Schubert-While
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