From: Margit Schubert-While <margit@margit.com>
To: linux-kernel@vger.kernel.org
Subject: L1_CACHE_SHIFT value for P4 ?
Date: Thu, 21 Nov 2002 15:39:33 +0100 [thread overview]
Message-ID: <4.3.2.7.2.20021121153829.00b5c7a0@mail.dns-host.com> (raw)
Just for the record - my x86info
Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 64 entries.
Data TLB: 4KB or 4MB pages, fully associative, 64 entries.
L1 Data cache:
Size: 8KB Sectored, 4-way associative.
line size=64 bytes.
No L3 cache
Instruction trace cache:
Size: 12K uOps 8-way associative.
L2 unified cache:
Size: 512KB Sectored, 8-way associative.
line size=64 bytes.
next reply other threads:[~2002-11-21 14:32 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-11-21 14:39 Margit Schubert-While [this message]
-- strict thread matches above, loose matches on Subject: below --
2002-11-21 13:25 Margit Schubert-While
2002-11-21 13:30 ` Dave Jones
[not found] <4.3.2.7.2.20021121130236.00b15370@mail.dns-host.com.suse.lists.linux.kernel>
2002-11-21 13:10 ` Andi Kleen
2002-11-21 13:23 ` Dave Jones
2002-11-21 13:42 ` Andi Kleen
2002-11-21 13:47 ` Dave Jones
2002-11-21 15:03 ` Mikael Pettersson
2002-11-21 12:13 Margit Schubert-While
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