* [PATCH v3 1/3] clk: qcom: dispcc-sm8450: Fix disp_cc_mdss_mdp_clk_src ops
2026-07-14 3:28 [PATCH v3 0/3] SM8450 QoL changes (dispcc) Esteban Urrutia via B4 Relay
@ 2026-07-14 3:28 ` Esteban Urrutia via B4 Relay
2026-07-17 21:02 ` David Heidelberg
2026-07-14 3:28 ` [PATCH v3 2/3] clk: qcom: dispcc-sm8450: Migrate to qcom_cc_driver_data Esteban Urrutia via B4 Relay
2026-07-14 3:28 ` [PATCH v3 3/3] clk: qcom: alpha-pll: Check Lucid Ole PLL status before configuring Esteban Urrutia via B4 Relay
2 siblings, 1 reply; 6+ messages in thread
From: Esteban Urrutia via B4 Relay @ 2026-07-14 3:28 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Brian Masney,
Dmitry Baryshkov, Jagadeesh Kona
Cc: linux-arm-msm, linux-clk, linux-kernel, phone-devel,
Esteban Urrutia, Konrad Dybcio
From: Esteban Urrutia <esteuwu@proton.me>
If the clock frequency is changed at registration time, a flicker will be
visible at boot.
Switching to clk_rcg2_shared_no_init_park_ops fixes this.
Fixes: 16fb89f92ec4 ("clk: qcom: Add support for Display Clock Controller on SM8450")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Esteban Urrutia <esteuwu@proton.me>
---
drivers/clk/qcom/dispcc-sm8450.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c
index 3af120e54cdd..c7e04bd315d5 100644
--- a/drivers/clk/qcom/dispcc-sm8450.c
+++ b/drivers/clk/qcom/dispcc-sm8450.c
@@ -613,7 +613,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
- .ops = &clk_rcg2_shared_ops,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
},
};
--
2.55.0
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v3 2/3] clk: qcom: dispcc-sm8450: Migrate to qcom_cc_driver_data
2026-07-14 3:28 [PATCH v3 0/3] SM8450 QoL changes (dispcc) Esteban Urrutia via B4 Relay
2026-07-14 3:28 ` [PATCH v3 1/3] clk: qcom: dispcc-sm8450: Fix disp_cc_mdss_mdp_clk_src ops Esteban Urrutia via B4 Relay
@ 2026-07-14 3:28 ` Esteban Urrutia via B4 Relay
2026-07-14 3:28 ` [PATCH v3 3/3] clk: qcom: alpha-pll: Check Lucid Ole PLL status before configuring Esteban Urrutia via B4 Relay
2 siblings, 0 replies; 6+ messages in thread
From: Esteban Urrutia via B4 Relay @ 2026-07-14 3:28 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Brian Masney,
Dmitry Baryshkov, Jagadeesh Kona
Cc: linux-arm-msm, linux-clk, linux-kernel, phone-devel,
Esteban Urrutia, Konrad Dybcio
From: Esteban Urrutia <esteuwu@proton.me>
Migrate to qcom_cc_driver_data, which is used by other clock controller
drivers.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Esteban Urrutia <esteuwu@proton.me>
---
drivers/clk/qcom/dispcc-sm8450.c | 38 ++++++++++++++++++++++++++++----------
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c
index c7e04bd315d5..facbf040ab9a 100644
--- a/drivers/clk/qcom/dispcc-sm8450.c
+++ b/drivers/clk/qcom/dispcc-sm8450.c
@@ -1778,6 +1778,29 @@ static const struct regmap_config disp_cc_sm8450_regmap_config = {
.fast_io = true,
};
+static struct clk_alpha_pll *disp_cc_sm8450_plls[] = {
+ &disp_cc_pll0,
+ &disp_cc_pll1,
+};
+
+static const u32 disp_cc_sm8450_critical_cbcrs[] = {
+ 0xe05c, /* DISP_CC_XO_CLK */
+};
+
+static void disp_cc_sm8450_clk_regs_configure(struct device *dev, struct regmap *regmap)
+{
+ /* Enable clock gating for MDP clocks */
+ regmap_set_bits(regmap, DISP_CC_MISC_CMD, BIT(4));
+}
+
+static const struct qcom_cc_driver_data disp_cc_sm8450_driver_data = {
+ .alpha_plls = disp_cc_sm8450_plls,
+ .num_alpha_plls = ARRAY_SIZE(disp_cc_sm8450_plls),
+ .clk_cbcrs = disp_cc_sm8450_critical_cbcrs,
+ .num_clk_cbcrs = ARRAY_SIZE(disp_cc_sm8450_critical_cbcrs),
+ .clk_regs_configure = disp_cc_sm8450_clk_regs_configure,
+};
+
static const struct qcom_cc_desc disp_cc_sm8450_desc = {
.config = &disp_cc_sm8450_regmap_config,
.clks = disp_cc_sm8450_clocks,
@@ -1786,6 +1809,7 @@ static const struct qcom_cc_desc disp_cc_sm8450_desc = {
.num_resets = ARRAY_SIZE(disp_cc_sm8450_resets),
.gdscs = disp_cc_sm8450_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sm8450_gdscs),
+ .driver_data = &disp_cc_sm8450_driver_data,
};
static const struct of_device_id disp_cc_sm8450_match_table[] = {
@@ -1823,19 +1847,13 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev)
disp_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
disp_cc_pll1.clkr.hw.init = &sm8475_disp_cc_pll1_init;
- clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &sm8475_disp_cc_pll0_config);
- clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &sm8475_disp_cc_pll1_config);
+ disp_cc_pll0.config = &sm8475_disp_cc_pll0_config;
+ disp_cc_pll1.config = &sm8475_disp_cc_pll1_config;
} else {
- clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
- clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
+ disp_cc_pll0.config = &disp_cc_pll0_config;
+ disp_cc_pll1.config = &disp_cc_pll1_config;
}
- /* Enable clock gating for MDP clocks */
- regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
-
- /* Keep some clocks always-on */
- qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */
-
ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8450_desc, regmap);
if (ret)
goto err_put_rpm;
--
2.55.0
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v3 3/3] clk: qcom: alpha-pll: Check Lucid Ole PLL status before configuring
2026-07-14 3:28 [PATCH v3 0/3] SM8450 QoL changes (dispcc) Esteban Urrutia via B4 Relay
2026-07-14 3:28 ` [PATCH v3 1/3] clk: qcom: dispcc-sm8450: Fix disp_cc_mdss_mdp_clk_src ops Esteban Urrutia via B4 Relay
2026-07-14 3:28 ` [PATCH v3 2/3] clk: qcom: dispcc-sm8450: Migrate to qcom_cc_driver_data Esteban Urrutia via B4 Relay
@ 2026-07-14 3:28 ` Esteban Urrutia via B4 Relay
2026-07-15 9:31 ` Konrad Dybcio
2 siblings, 1 reply; 6+ messages in thread
From: Esteban Urrutia via B4 Relay @ 2026-07-14 3:28 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Brian Masney,
Dmitry Baryshkov, Jagadeesh Kona
Cc: linux-arm-msm, linux-clk, linux-kernel, phone-devel, Esteban Urrutia
From: Esteban Urrutia <esteuwu@proton.me>
On some platforms such as SM8475, not doing this may result in graphical
glitches when the mdss driver takes over.
This fixes the aforementioned issue.
Fixes: 3132a9a11e57 ("clk: qcom: clk-alpha-pll: Add support for lucid ole pll configure")
Signed-off-by: Esteban Urrutia <esteuwu@proton.me>
---
drivers/clk/qcom/clk-alpha-pll.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index f8313f9d0e30..60173b076cc5 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -2373,6 +2373,15 @@ void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma
{
u32 lval = config->l;
+ /*
+ * If the bootloader left the PLL enabled it's likely that there are
+ * RCGs that will lock up if we disable the PLL below.
+ */
+ if (trion_pll_is_enabled(pll, regmap)) {
+ pr_debug("Lucid Ole PLL is already enabled, skipping configuration\n");
+ return;
+ }
+
lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
lval |= TRION_PLL_CAL_VAL << LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT;
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
--
2.55.0
^ permalink raw reply [flat|nested] 6+ messages in thread