[PATCH v2 0/3] arm64: dts: marvell: Add Sophos XGS 107w NPU

[PATCH v2 0/3] arm64: dts: marvell: Add Sophos XGS 107w NPU

[Nicolo Giuliani via B4 Relay]

The Sophos XGS 87/107 desktop firewalls pair an AMD x86 host with a
separate network processing unit (NPU): a Marvell Armada CN9130 SoC with
its own eMMC and SPI NOR flash. The NPU serves the eight RJ45 ports and
the SFP cage through a Marvell 88E6193X switch on its MDIO bus, which is
connected to the SoC by a 10GBASE-R link, and reaches the x86 host over
PCIe.

This series adds the Sophos vendor prefix, the compatible string of the
NPU board and a device tree that describes the NPU as a standalone system:
UART console, eMMC, SPI NOR flash, the SFP cage and the switch with its
ports. The port LEDs, the USB ports and the PCIe link to the x86 host (the
CN9130 acts as a PCIe endpoint towards it, which needs endpoint support
that is not part of this series) are not described.

Tested on an XGS 107w with Linux 6.18: boot from eMMC, eMMC and SPI NOR
access, the mvpp2 link to the switch at 10 Gb/s, the 88E6193X probing with
its eight user ports, and 936 Mbit/s through a front port. The SFP cage
is untested.

dt_binding_check passes for vendor-prefixes.yaml and armada-7k-8k.yaml,
and CHECK_DTBS=y on marvell/cn9130-sophos-xgs107w.dtb reports no warning
specific to this board.

Based on the mvebu/dt branch of the mvebu tree (008e9faade).

Signed-off-by: Nicolo Giuliani <nicolo.giuliani6@studio.unibo.it>
---
Changes in v2:
- Patch 1: drop the second sentence of the commit message, add Acked-by
- Patch 2: move the entry before the SolidRun ones and list only
  marvell,cn9130 after the board compatible, as the other CN9130 boards do
- Patch 3: use the compatible list of patch 2; pass the switch reset as
  reset-gpios and drop the boot loader workaround; remove the LED
  expander node and the SFP address comment
- Link to v1: https://patch.msgid.link/20260919-send-dt-v1-0-365615a74ef3@studio.unibo.it

---
Nicolo Giuliani (3):
      dt-bindings: vendor-prefixes: Add Sophos
      dt-bindings: arm: marvell: Add Sophos XGS 107w NPU
      arm64: dts: marvell: Add Sophos XGS 107w NPU board

 .../bindings/arm/marvell/armada-7k-8k.yaml         |   7 +
 .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
 arch/arm64/boot/dts/marvell/Makefile               |   1 +
 .../boot/dts/marvell/cn9130-sophos-xgs107w.dts     | 188 +++++++++++++++++++++
 4 files changed, 198 insertions(+)
---
base-commit: 008e9faadef8c0aaa9b8a3ff05a2126e3c5b08b7
change-id: 20260919-send-dt-6bbd08a470d2

Best regards,
--  
Nicolo Giuliani <nicolo.giuliani6@studio.unibo.it>

[PATCH v2 1/3] dt-bindings: vendor-prefixes: Add Sophos

[Nicolo Giuliani via B4 Relay]

From: Nicolo Giuliani <nicolo.giuliani6@studio.unibo.it>

Add the "sophos" vendor prefix for Sophos Ltd., a vendor of network
security appliances.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Assisted-by: LLM
Signed-off-by: Nicolo Giuliani <nicolo.giuliani6@studio.unibo.it>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index ba20029693..3dd9d9b8ab 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1595,6 +1595,8 @@ patternProperties:
     description: Sony Corporation
   "^sophgo,.*":
     description: Sophgo Technology Inc.
+  "^sophos,.*":
+    description: Sophos Ltd.
   "^sourceparts,.*":
     description: Source Parts Inc.
   "^spacemit,.*":

-- 
2.48.1

[PATCH v2 2/3] dt-bindings: arm: marvell: Add Sophos XGS 107w NPU

[Nicolo Giuliani via B4 Relay]

From: Nicolo Giuliani <nicolo.giuliani6@studio.unibo.it>

The Sophos XGS 87/107 desktop firewalls combine an AMD x86 host with a
separate network processing unit (NPU). The NPU is a Marvell Armada CN9130
SoC with its own eMMC and SPI NOR flash, connected to the x86 host over
PCIe. It serves the front panel ports through a Marvell 88E6193X switch.

Document the compatible string of the NPU board, with the CN9130 SoC
compatibles as fallbacks.

Assisted-by: LLM
Signed-off-by: Nicolo Giuliani <nicolo.giuliani6@studio.unibo.it>
---
 Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
index 7e77310da6..130128c462 100644
--- a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
+++ b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
@@ -118,6 +118,13 @@ properties:
           - const: marvell,armada-ap807-quad
           - const: marvell,armada-ap807
 
+      - description:
+          Sophos XGS 87/107 network processing unit (Armada CN9130 SoC
+          with an 88E6193X switch)
+        items:
+          - const: sophos,xgs107w-npu
+          - const: marvell,cn9130
+
       - description:
           SolidRun CN9130 SoM based single-board computers
         items:

-- 
2.48.1

[PATCH v2 3/3] arm64: dts: marvell: Add Sophos XGS 107w NPU board

[Nicolo Giuliani via B4 Relay]

From: Nicolo Giuliani <nicolo.giuliani6@studio.unibo.it>

Add a device tree for the network processing unit (NPU) of the Sophos
XGS 87/107 desktop firewalls. The appliance pairs an AMD x86 host with the
NPU, a Marvell Armada CN9130 SoC with its own eMMC and SPI NOR flash that
runs independently of the host and serves the front panel ports.

The eight RJ45 ports and the SFP cage are connected through a Marvell
88E6193X switch on the MDIO bus of the SoC, at address 2. Switch port 0
is the CPU port, a 10GBASE-R link to the first mvpp2 port. Ports 1 to 8
are the RJ45 ports, which use the internal PHYs of the switch, and
port 9 is the SFP cage, connected over 1000BASE-X.

Describe the UART console, the eMMC, the SPI NOR flash that holds the boot
loader and its environment (read-only), the SFP cage and the switch with
its ports. The port LEDs, the PCIe link to the x86 host and the USB ports
are not described.

The switch is reset through CP GPIO2 pin 17.

Tested on an XGS 107w with Linux 6.18: boot from eMMC, eMMC and SPI NOR
access, the mvpp2 link to the switch at 10 Gb/s, the 88E6193X probing with
its eight user ports, and 936 Mbit/s through a front port. The SFP cage is
untested.

Assisted-by: LLM
Signed-off-by: Nicolo Giuliani <nicolo.giuliani6@studio.unibo.it>
---
 arch/arm64/boot/dts/marvell/Makefile               |   1 +
 .../boot/dts/marvell/cn9130-sophos-xgs107w.dts     | 188 +++++++++++++++++++++
 2 files changed, 189 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index 09d1544041..3e301c8265 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -32,6 +32,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += ac5x-rd-carrier-cn9131.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-base.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-pro.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-sophos-xgs107w.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += cn9131-cf-solidwan.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += cn9132-clearfog.dtb
 
diff --git a/arch/arm64/boot/dts/marvell/cn9130-sophos-xgs107w.dts b/arch/arm64/boot/dts/marvell/cn9130-sophos-xgs107w.dts
new file mode 100644
index 0000000000..da6a1da1cc
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-sophos-xgs107w.dts
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device tree for the network processing unit (NPU) of the Sophos XGS 87/107
+ * firewalls: a Marvell CN9130 SoC with a Marvell 88E6193X switch.
+ *
+ * The x86 host on the same board is not described here.
+ */
+
+/dts-v1/;
+
+#include "cn9130.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Sophos XGS 107w (CN9130 NPU)";
+	compatible = "sophos,xgs107w-npu", "marvell,cn9130";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		ethernet0 = &cp0_eth0;
+		i2c1 = &cp0_i2c1;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+
+	reserved-memory {
+		/* OP-TEE, reserved by the firmware */
+		tee@4400000 {
+			reg = <0x0 0x4400000 0x0 0x1000000>;
+			no-map;
+		};
+	};
+
+	/* Front-panel SFP cage "F1", wired to switch port 9 */
+	sfp: sfp {
+		compatible = "sff,sfp";
+		i2c-bus = <&cp0_i2c1>;
+		los-gpios = <&cp0_gpio1 1 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpios = <&cp0_gpio1 2 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&cp0_gpio1 3 GPIO_ACTIVE_LOW>;
+		tx-disable-gpios = <&cp0_gpio1 7 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+/* eMMC on the AP */
+&ap_sdhci0 {
+	bus-width = <8>;
+	non-removable;
+	mmc-ddr-1_8v;
+	status = "okay";
+};
+
+/*
+ * The MPP pin muxing is left as configured by the boot loader; the pin
+ * controller node only exists to back the GPIO banks.
+ */
+&cp0_syscon0 {
+	cp0_pinctrl: pinctrl {
+		compatible = "marvell,cp115-standalone-pinctrl";
+	};
+};
+
+&cp0_i2c1 {
+	/* I2C bus of the SFP cage */
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+/* 4 MB SPI NOR with U-Boot and its environment, read-only on purpose */
+&cp0_spi0 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <40000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x0 0x3f0000>;
+				read-only;
+			};
+
+			partition@3f0000 {
+				label = "u-boot-env";
+				reg = <0x3f0000 0x10000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&cp0_ethernet {
+	status = "okay";
+};
+
+/* 10G link to switch port 0 */
+&cp0_eth0 {
+	phy-mode = "10gbase-r";
+	phys = <&cp0_comphy4 0>;
+	managed = "in-band-status";
+	status = "okay";
+};
+
+&cp0_mdio {
+	status = "okay";
+
+	switch@2 {
+		compatible = "marvell,mv88e6190";
+		reg = <2>;
+		reset-gpios = <&cp0_gpio2 17 GPIO_ACTIVE_LOW>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				ethernet = <&cp0_eth0>;
+				phy-mode = "10gbase-r";
+				managed = "in-band-status";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "p1";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "p2";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "p3";
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "p4";
+			};
+
+			port@5 {
+				reg = <5>;
+				label = "p5";
+			};
+
+			port@6 {
+				reg = <6>;
+				label = "p6";
+			};
+
+			port@7 {
+				reg = <7>;
+				label = "p7";
+			};
+
+			port@8 {
+				reg = <8>;
+				label = "p8";
+			};
+
+			port@9 {
+				reg = <9>;
+				label = "sfp";
+				phy-mode = "1000base-x";
+				managed = "in-band-status";
+				sfp = <&sfp>;
+			};
+		};
+	};
+};

-- 
2.48.1

Re: [PATCH v2 3/3] arm64: dts: marvell: Add Sophos XGS 107w NPU board

[Andrew Lunn]

On Mon, Sep 21, 2026 at 02:26:43AM +0200, Nicolo Giuliani via B4 Relay wrote:
> From: Nicolo Giuliani <nicolo.giuliani6@studio.unibo.it>
> 
> Add a device tree for the network processing unit (NPU) of the Sophos
> XGS 87/107 desktop firewalls. The appliance pairs an AMD x86 host with the
> NPU, a Marvell Armada CN9130 SoC with its own eMMC and SPI NOR flash that
> runs independently of the host and serves the front panel ports.
> 
> The eight RJ45 ports and the SFP cage are connected through a Marvell
> 88E6193X switch on the MDIO bus of the SoC, at address 2. Switch port 0
> is the CPU port, a 10GBASE-R link to the first mvpp2 port. Ports 1 to 8
> are the RJ45 ports, which use the internal PHYs of the switch, and
> port 9 is the SFP cage, connected over 1000BASE-X.
> 
> Describe the UART console, the eMMC, the SPI NOR flash that holds the boot
> loader and its environment (read-only), the SFP cage and the switch with
> its ports. The port LEDs, the PCIe link to the x86 host and the USB ports
> are not described.
> 
> The switch is reset through CP GPIO2 pin 17.
> 
> Tested on an XGS 107w with Linux 6.18: boot from eMMC, eMMC and SPI NOR
> access, the mvpp2 link to the switch at 10 Gb/s, the 88E6193X probing with
> its eight user ports, and 936 Mbit/s through a front port. The SFP cage is
> untested.
> 
> Assisted-by: LLM
> Signed-off-by: Nicolo Giuliani <nicolo.giuliani6@studio.unibo.it>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH v2 2/3] dt-bindings: arm: marvell: Add Sophos XGS 107w NPU

[Krzysztof Kozlowski]

On Mon, Sep 21, 2026 at 02:26:42AM +0200, Nicolo Giuliani wrote:
> The Sophos XGS 87/107 desktop firewalls combine an AMD x86 host with a
> separate network processing unit (NPU). The NPU is a Marvell Armada CN9130
> SoC with its own eMMC and SPI NOR flash, connected to the x86 host over
> PCIe. It serves the front panel ports through a Marvell 88E6193X switch.
> 
> Document the compatible string of the NPU board, with the CN9130 SoC
> compatibles as fallbacks.
> 
> Assisted-by: LLM
> Signed-off-by: Nicolo Giuliani <nicolo.giuliani6@studio.unibo.it>
> ---
>  Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
> 

I don't know which fallbacks are right, why cn9130 sometimes has,
sometimes does not, I guess Marvell maintainers will sort it out:

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

R: [PATCH v2 0/3] arm64: dts: marvell: Add Sophos XGS 107w NPU

[Nicolò Giuliani - nicolo.giuliani6@studio.unibo.it]

Hi Gregory, Andrew, Sebastian,

This series has Acked-by from Krzysztof on 1/3 and 2/3, and Reviewed-by from Andrew on 3/3. Is there anything else needed before it can be applied, or should I wait for the next merge window?

Thanks,
Nicolo Giuliani

________________________________________
Da: Nicolo Giuliani via B4 Relay <devnull+nicolo.giuliani6.studio.unibo.it@kernel.org>
Inviato: lunedì 21 settembre 2026 02:26
A: Rob Herring; Krzysztof Kozlowski; Conor Dooley; Andrew Lunn; Gregory Clement; Sebastian Hesselbarth
Cc: devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Nicolò Giuliani - nicolo.giuliani6@studio.unibo.it; Krzysztof Kozlowski
Oggetto: [PATCH v2 0/3] arm64: dts: marvell: Add Sophos XGS 107w NPU

The Sophos XGS 87/107 desktop firewalls pair an AMD x86 host with a
separate network processing unit (NPU): a Marvell Armada CN9130 SoC with
its own eMMC and SPI NOR flash. The NPU serves the eight RJ45 ports and
the SFP cage through a Marvell 88E6193X switch on its MDIO bus, which is
connected to the SoC by a 10GBASE-R link, and reaches the x86 host over
PCIe.

This series adds the Sophos vendor prefix, the compatible string of the
NPU board and a device tree that describes the NPU as a standalone system:
UART console, eMMC, SPI NOR flash, the SFP cage and the switch with its
ports. The port LEDs, the USB ports and the PCIe link to the x86 host (the
CN9130 acts as a PCIe endpoint towards it, which needs endpoint support
that is not part of this series) are not described.

Tested on an XGS 107w with Linux 6.18: boot from eMMC, eMMC and SPI NOR
access, the mvpp2 link to the switch at 10 Gb/s, the 88E6193X probing with
its eight user ports, and 936 Mbit/s through a front port. The SFP cage
is untested.

dt_binding_check passes for vendor-prefixes.yaml and armada-7k-8k.yaml,
and CHECK_DTBS=y on marvell/cn9130-sophos-xgs107w.dtb reports no warning
specific to this board.

Based on the mvebu/dt branch of the mvebu tree (008e9faade).

Signed-off-by: Nicolo Giuliani <nicolo.giuliani6@studio.unibo.it>
---
Changes in v2:
- Patch 1: drop the second sentence of the commit message, add Acked-by
- Patch 2: move the entry before the SolidRun ones and list only
  marvell,cn9130 after the board compatible, as the other CN9130 boards do
- Patch 3: use the compatible list of patch 2; pass the switch reset as
  reset-gpios and drop the boot loader workaround; remove the LED
  expander node and the SFP address comment
- Link to v1: https://patch.msgid.link/20260919-send-dt-v1-0-365615a74ef3@studio.unibo.it

---
Nicolo Giuliani (3):
      dt-bindings: vendor-prefixes: Add Sophos
      dt-bindings: arm: marvell: Add Sophos XGS 107w NPU
      arm64: dts: marvell: Add Sophos XGS 107w NPU board

 .../bindings/arm/marvell/armada-7k-8k.yaml         |   7 +
 .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
 arch/arm64/boot/dts/marvell/Makefile               |   1 +
 .../boot/dts/marvell/cn9130-sophos-xgs107w.dts     | 188 +++++++++++++++++++++
 4 files changed, 198 insertions(+)
---
base-commit: 008e9faadef8c0aaa9b8a3ff05a2126e3c5b08b7
change-id: 20260919-send-dt-6bbd08a470d2

Best regards,
--
Nicolo Giuliani <nicolo.giuliani6@studio.unibo.it>

Re: R: [PATCH v2 0/3] arm64: dts: marvell: Add Sophos XGS 107w NPU

[Gregory Clement]

On Wednesday, September 30, 2026 10:35 CEST, Nicolò Giuliani - nicolo.giuliani6@studio.unibo.it <nicolo.giuliani6@studio.unibo.it> wrote:

> 
> Hi Gregory, Andrew, Sebastian,
Hello  Nicolo,

> This series has Acked-by from Krzysztof on 1/3 and 2/3, and Reviewed-by from Andrew on 3/3. Is there anything else needed before it can be applied, or should I wait for the next merge window?

I am working on the backlog today, either I will apply it or I will let know if something is missing.

Gregory

> 
> Thanks,
> Nicolo Giuliani
> 
> ________________________________________
> Da: Nicolo Giuliani via B4 Relay <devnull+nicolo.giuliani6.studio.unibo.it@kernel.org>
> Inviato: lunedì 21 settembre 2026 02:26
> A: Rob Herring; Krzysztof Kozlowski; Conor Dooley; Andrew Lunn; Gregory Clement; Sebastian Hesselbarth
> Cc: devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Nicolò Giuliani - nicolo.giuliani6@studio.unibo.it; Krzysztof Kozlowski
> Oggetto: [PATCH v2 0/3] arm64: dts: marvell: Add Sophos XGS 107w NPU
> 
> The Sophos XGS 87/107 desktop firewalls pair an AMD x86 host with a
> separate network processing unit (NPU): a Marvell Armada CN9130 SoC with
> its own eMMC and SPI NOR flash. The NPU serves the eight RJ45 ports and
> the SFP cage through a Marvell 88E6193X switch on its MDIO bus, which is
> connected to the SoC by a 10GBASE-R link, and reaches the x86 host over
> PCIe.
> 
> This series adds the Sophos vendor prefix, the compatible string of the
> NPU board and a device tree that describes the NPU as a standalone system:
> UART console, eMMC, SPI NOR flash, the SFP cage and the switch with its
> ports. The port LEDs, the USB ports and the PCIe link to the x86 host (the
> CN9130 acts as a PCIe endpoint towards it, which needs endpoint support
> that is not part of this series) are not described.
> 
> Tested on an XGS 107w with Linux 6.18: boot from eMMC, eMMC and SPI NOR
> access, the mvpp2 link to the switch at 10 Gb/s, the 88E6193X probing with
> its eight user ports, and 936 Mbit/s through a front port. The SFP cage
> is untested.
> 
> dt_binding_check passes for vendor-prefixes.yaml and armada-7k-8k.yaml,
> and CHECK_DTBS=y on marvell/cn9130-sophos-xgs107w.dtb reports no warning
> specific to this board.
> 
> Based on the mvebu/dt branch of the mvebu tree (008e9faade).
> 
> Signed-off-by: Nicolo Giuliani <nicolo.giuliani6@studio.unibo.it>
> ---
> Changes in v2:
> - Patch 1: drop the second sentence of the commit message, add Acked-by
> - Patch 2: move the entry before the SolidRun ones and list only
>   marvell,cn9130 after the board compatible, as the other CN9130 boards do
> - Patch 3: use the compatible list of patch 2; pass the switch reset as
>   reset-gpios and drop the boot loader workaround; remove the LED
>   expander node and the SFP address comment
> - Link to v1: https://patch.msgid.link/20260919-send-dt-v1-0-365615a74ef3@studio.unibo.it
> 
> ---
> Nicolo Giuliani (3):
>       dt-bindings: vendor-prefixes: Add Sophos
>       dt-bindings: arm: marvell: Add Sophos XGS 107w NPU
>       arm64: dts: marvell: Add Sophos XGS 107w NPU board
> 
>  .../bindings/arm/marvell/armada-7k-8k.yaml         |   7 +
>  .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
>  arch/arm64/boot/dts/marvell/Makefile               |   1 +
>  .../boot/dts/marvell/cn9130-sophos-xgs107w.dts     | 188 +++++++++++++++++++++
>  4 files changed, 198 insertions(+)
> ---
> base-commit: 008e9faadef8c0aaa9b8a3ff05a2126e3c5b08b7
> change-id: 20260919-send-dt-6bbd08a470d2
> 
> Best regards,
> --
> Nicolo Giuliani <nicolo.giuliani6@studio.unibo.it>
> 
>