Re: [PATCH 2/2] x86/bugs: Don't fill RSB on context switch with eIBRS

["Shah, Amit" <Amit.Shah@amd.com>]

On Tue, 2024-11-19 at 23:27 -0800, Josh Poimboeuf wrote:


[...]

> @@ -1617,12 +1634,13 @@ static void __init
> spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_
>  	case SPECTRE_V2_RETPOLINE:
>  	case SPECTRE_V2_LFENCE:
>  	case SPECTRE_V2_IBRS:
> -		pr_info("Spectre v2 / SpectreRSB : Filling RSB on
> VMEXIT\n");
> +		pr_info("Spectre v2 / SpectreRSB : Filling RSB on
> context switch and VMEXIT\n");

Nit: stray whitespace before ':'

> +		setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
>  		setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT);
>  		return;
>  	}
>  
> -	pr_warn_once("Unknown Spectre v2 mode, disabling RSB
> mitigation at VM exit");
> +	pr_warn_once("Unknown Spectre v2 mode, disabling RSB
> mitigation\n");
>  	dump_stack();

For the ERAPS patches, they'll flow better if these two lines are
within a 'default' switch statement (with the other returns changing to
breaks).  I can do that, of course, but if you need to spin a v2 and
update that, it'll save some churn.

Thanks,

		Amit