From: Rik van Riel <riel@surriel.com>
To: kernel test robot <lkp@intel.com>
Cc: llvm <llvm@lists.linux.dev>, x86 <x86@kernel.org>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>,
kernel-team <kernel-team@meta.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v5 05/12] x86/mm: add INVLPGB support code
Date: Fri, 17 Jan 2025 09:20:13 -0500 [thread overview]
Message-ID: <44837964d67d6f35a20139fbe310f621141a0404.camel@surriel.com> (raw)
In-Reply-To: <202501171121.nQcwVI41-lkp@intel.com>
On Fri, 2025-01-17 at 11:37 +0800, kernel test robot wrote:
>
> compiler: clang version 19.1.3
> (https://github.com/llvm/llvm-project ab51eccf88f5321e7c60591c5546b25
> 4b6afab99)
> reproduce (this is a W=1 build):
> (https://download.01.org/0day-ci/archive/20250117/202501171121.nQcwVI
> 41-lkp@intel.com/reproduce)
>
> > > arch/x86/include/asm/invlpgb.h:26:49: error: invalid input size
> > > for constraint 'a'
> 26 | asm volatile(".byte 0x0f, 0x01, 0xfe" : : "a"
> (rax), "c" (ecx), "d" (edx));
> | ^
>
What do I do about this?
It didn't used to complain when we had a named
assembler operator there:
asm volatile("invlpgb" : : "a" (rax), "c" (ecx), "d" (edx));
However, now that we're using .byte for compatibility
with older binutils, things break with newer llvm?
--
All Rights Reversed.
next prev parent reply other threads:[~2025-01-17 14:20 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-16 2:30 [PATCH v5 00/12] AMD broadcast TLB invalidation Rik van Riel
2025-01-16 2:30 ` [PATCH v5 01/12] x86/mm: make MMU_GATHER_RCU_TABLE_FREE unconditional Rik van Riel
2025-01-16 2:30 ` [PATCH v5 02/12] x86/mm: remove pv_ops.mmu.tlb_remove_table call Rik van Riel
2025-01-16 2:30 ` [PATCH v5 03/12] x86/mm: consolidate full flush threshold decision Rik van Riel
2025-01-17 19:23 ` Michael Kelley
2025-01-17 19:32 ` Rik van Riel
2025-01-16 2:30 ` [PATCH v5 04/12] x86/mm: get INVLPGB count max from CPUID Rik van Riel
2025-01-16 2:30 ` [PATCH v5 05/12] x86/mm: add INVLPGB support code Rik van Riel
[not found] ` <202501171121.nQcwVI41-lkp@intel.com>
2025-01-17 14:20 ` Rik van Riel [this message]
2025-01-17 15:01 ` Rik van Riel
2025-01-16 2:30 ` [PATCH v5 06/12] x86/mm: use INVLPGB for kernel TLB flushes Rik van Riel
2025-01-16 2:30 ` [PATCH v5 07/12] x86/tlb: use INVLPGB in flush_tlb_all Rik van Riel
2025-01-16 2:30 ` [PATCH v5 08/12] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2025-01-16 2:30 ` [PATCH v5 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2025-01-16 2:30 ` [PATCH v5 10/12] x86,tlb: do targeted broadcast flushing from tlbbatch code Rik van Riel
2025-01-20 9:56 ` Nadav Amit
2025-01-20 14:02 ` Rik van Riel
2025-01-20 14:14 ` Nadav Amit
2025-01-20 16:11 ` Rik van Riel
2025-01-20 17:09 ` Nadav Amit
2025-01-20 17:11 ` Rik van Riel
2025-01-20 17:50 ` Nadav Amit
2025-01-20 17:56 ` Rik van Riel
2025-01-20 18:56 ` Nadav Amit
2025-01-21 2:33 ` Rik van Riel
2025-01-16 2:30 ` [PATCH v5 11/12] x86/mm: enable AMD translation cache extensions Rik van Riel
2025-01-16 2:30 ` [PATCH v5 12/12] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2025-01-16 18:14 ` [PATCH v5 00/12] AMD broadcast TLB invalidation Michael Kelley
2025-01-16 22:37 ` Peter Zijlstra
2025-01-17 0:00 ` Andrew Cooper
2025-01-21 10:45 ` Peter Zijlstra
2025-01-21 17:14 ` Dave Hansen
2025-01-21 21:24 ` Michael Kelley
2025-01-21 17:22 ` Jann Horn
2025-01-21 21:39 ` Michael Kelley
2025-01-21 21:56 ` Jann Horn
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