From: Rik van Riel <riel@surriel.com>
To: Nadav Amit <nadav.amit@gmail.com>
Cc: the arch/x86 maintainers <x86@kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Borislav Petkov <bp@alien8.de>,
peterz@infradead.org, Dave Hansen <dave.hansen@linux.intel.com>,
zhengqi.arch@bytedance.com, thomas.lendacky@amd.com,
kernel-team@meta.com,
"open list:MEMORY MANAGEMENT" <linux-mm@kvack.org>,
Andrew Morton <akpm@linux-foundation.org>,
jannh@google.com, mhklinux@outlook.com,
andrew.cooper3@citrix.com
Subject: Re: [PATCH v5 10/12] x86,tlb: do targeted broadcast flushing from tlbbatch code
Date: Mon, 20 Jan 2025 21:33:11 -0500 [thread overview]
Message-ID: <4994c1220ce4103bb354da46699a77c3a5dfa310.camel@surriel.com> (raw)
In-Reply-To: <5501C6EC-38C7-472F-B129-F7A5144C3096@gmail.com>
On Mon, 2025-01-20 at 20:56 +0200, Nadav Amit wrote:
>
> Then in switch_mm_irqs_off(), b
>
> if (this_cpu_read(cpu_tlbstate.pending_tlbsync))
> tlbsync();
>
> Note that when switch_mm_irqs_off() is called due to context switch
> from
> context_switch(), finish_task_switch() has still not took place, so
> the
> task cannot be scheduled on other cores.
>
>
That would certainly work.
I'll add that as a separate patch, which the x86
maintainers can either accept or leave out.
I'm not sure what's worse, making reclaim non-migratable,
or adding an extra branch (we can probably avoid a cache
line miss) to switch_mm_irqs_off.
--
All Rights Reversed.
next prev parent reply other threads:[~2025-01-21 2:33 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-16 2:30 [PATCH v5 00/12] AMD broadcast TLB invalidation Rik van Riel
2025-01-16 2:30 ` [PATCH v5 01/12] x86/mm: make MMU_GATHER_RCU_TABLE_FREE unconditional Rik van Riel
2025-01-16 2:30 ` [PATCH v5 02/12] x86/mm: remove pv_ops.mmu.tlb_remove_table call Rik van Riel
2025-01-16 2:30 ` [PATCH v5 03/12] x86/mm: consolidate full flush threshold decision Rik van Riel
2025-01-17 19:23 ` Michael Kelley
2025-01-17 19:32 ` Rik van Riel
2025-01-16 2:30 ` [PATCH v5 04/12] x86/mm: get INVLPGB count max from CPUID Rik van Riel
2025-01-16 2:30 ` [PATCH v5 05/12] x86/mm: add INVLPGB support code Rik van Riel
[not found] ` <202501171121.nQcwVI41-lkp@intel.com>
2025-01-17 14:20 ` Rik van Riel
2025-01-17 15:01 ` Rik van Riel
2025-01-16 2:30 ` [PATCH v5 06/12] x86/mm: use INVLPGB for kernel TLB flushes Rik van Riel
2025-01-16 2:30 ` [PATCH v5 07/12] x86/tlb: use INVLPGB in flush_tlb_all Rik van Riel
2025-01-16 2:30 ` [PATCH v5 08/12] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2025-01-16 2:30 ` [PATCH v5 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2025-01-16 2:30 ` [PATCH v5 10/12] x86,tlb: do targeted broadcast flushing from tlbbatch code Rik van Riel
2025-01-20 9:56 ` Nadav Amit
2025-01-20 14:02 ` Rik van Riel
2025-01-20 14:14 ` Nadav Amit
2025-01-20 16:11 ` Rik van Riel
2025-01-20 17:09 ` Nadav Amit
2025-01-20 17:11 ` Rik van Riel
2025-01-20 17:50 ` Nadav Amit
2025-01-20 17:56 ` Rik van Riel
2025-01-20 18:56 ` Nadav Amit
2025-01-21 2:33 ` Rik van Riel [this message]
2025-01-16 2:30 ` [PATCH v5 11/12] x86/mm: enable AMD translation cache extensions Rik van Riel
2025-01-16 2:30 ` [PATCH v5 12/12] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2025-01-16 18:14 ` [PATCH v5 00/12] AMD broadcast TLB invalidation Michael Kelley
2025-01-16 22:37 ` Peter Zijlstra
2025-01-17 0:00 ` Andrew Cooper
2025-01-21 10:45 ` Peter Zijlstra
2025-01-21 17:14 ` Dave Hansen
2025-01-21 21:24 ` Michael Kelley
2025-01-21 17:22 ` Jann Horn
2025-01-21 21:39 ` Michael Kelley
2025-01-21 21:56 ` Jann Horn
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