From: Philipp Zabel <p.zabel@pengutronix.de>
To: Changhuang Liang <changhuang.liang@starfivetech.com>,
Brian Masney <bmasney@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Emil Renner Berthing <kernel@esmil.dk>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org,
Hal Feng <hal.feng@starfivetech.com>
Subject: Re: [PATCH v6 14/15] reset: starfive: jh71x0: Support discontiguous reset IDs
Date: Thu, 12 Nov 2026 12:21:08 +0100 [thread overview]
Message-ID: <45683ba0cf239f394b621d84cbd5535f7eae410f.camel@pengutronix.de> (raw)
In-Reply-To: <20261008123338.11081-15-changhuang.liang@starfivetech.com>
On Do, 2026-10-08 at 05:33 -0700, Changhuang Liang wrote:
> The reset IDs exposed to consumers of the StarFive JHB100 reset
> controllers do not map one-to-one to the hardware reset bits.
>
> Add struct jh71x0_reset_info, which describes the number of resets, the
> assert/status register offsets and, for discontiguous controllers, a
> table mapping reset IDs to hardware bits. Add
> reset_starfive_jh71x0_register_with_info() to register such a
> controller, and translate the reset ID in the update and status
> callbacks when a map is provided.
>
> Existing users of reset_starfive_jh71x0_register() are unaffected.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
> .../reset/starfive/reset-starfive-jh71x0.c | 99 ++++++++++++++++---
> .../reset/starfive/reset-starfive-jh71x0.h | 19 ++++
> 2 files changed, 107 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-jh71x0.c
> index 29ce3486752f..fd1c755a0017 100644
> --- a/drivers/reset/starfive/reset-starfive-jh71x0.c
> +++ b/drivers/reset/starfive/reset-starfive-jh71x0.c
[...]
> @@ -29,19 +36,40 @@ jh71x0_reset_from(struct reset_controller_dev *rcdev)
> return container_of(rcdev, struct jh71x0_reset, rcdev);
> }
>
> +static unsigned long
> +jh71x0_reset_id_to_hw_id(const struct jh71x0_reset_map *map, unsigned int nr_resets,
> + unsigned long reset_id)
> +{
> + for (u32 i = 0; i < nr_resets; i++) {
> + if (map[i].reset_id == reset_id)
> + return map[i].hw_id;
> + }
> +
> + return JH71X0_RESET_ID_INVALID;
> +}
> +
> static int jh71x0_reset_update(struct reset_controller_dev *rcdev,
> unsigned long id, bool assert)
> {
> struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
> - unsigned long offset = id / 32;
> - u32 mask = BIT(id % 32);
> - void __iomem *reg_assert = data->assert + offset * sizeof(u32);
> - void __iomem *reg_status = data->status + offset * sizeof(u32);
> - u32 done = data->asserted ? data->asserted[offset] & mask : 0;
> - u32 value;
> - unsigned long flags;
> + unsigned long offset, flags;
> + void __iomem *reg_assert;
> + void __iomem *reg_status;
> + u32 mask, done, value;
> int ret;
>
> + if (data->info && data->info->discontiguous) {
> + id = jh71x0_reset_id_to_hw_id(data->info->map, data->info->nr_resets, id);
> + if (id == JH71X0_RESET_ID_INVALID)
> + return -EINVAL;
> + }
Why is this lookup done in the ops?
It should be done once in fwnode_xlate instead.
> +
> + offset = id / 32;
> + mask = BIT(id % 32);
> + reg_assert = data->assert + offset * sizeof(u32);
> + reg_status = data->status + offset * sizeof(u32);
> + done = data->asserted ? data->asserted[offset] & mask : 0;
> +
> if (!assert)
> done ^= mask;
>
>
[...]
> @@ -132,3 +170,42 @@ int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_no
> return devm_reset_controller_register(dev, &data->rcdev);
> }
> EXPORT_SYMBOL_GPL(reset_starfive_jh71x0_register);
> +
> +int reset_starfive_jh71x0_register_with_info(struct device *dev, struct device_node *of_node,
> + void __iomem *assert, void __iomem *status,
> + const u32 *asserted,
> + const struct jh71x0_reset_info *info,
> + struct module *owner)
> +{
> + struct jh71x0_reset *data;
> + int ret;
> +
> + if (info->discontiguous && (!info->map || !info->nr_resets))
> + return dev_err_probe(dev, -EINVAL,
> + "discontiguous controller without a valid ID map\n");
> +
> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + data->rcdev.ops = &jh71x0_reset_ops;
> + data->rcdev.owner = owner;
> + data->rcdev.nr_resets = info->nr_resets;
> + data->rcdev.dev = dev;
> + data->rcdev.of_node = of_node;
You can add a custom fwnode_xlate that does the
jh71x0_reset_id_to_hw_id() translation if info->map is set.
> +
> + spin_lock_init(&data->lock);
> + data->assert = assert;
> + data->status = status;
> + data->asserted = asserted;
> + data->info = info;
> +
> + ret = devm_reset_controller_register(dev, &data->rcdev);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Failed to register reset controller\n");
> +
> + dev_info(dev, "Registered %u resets\n", data->rcdev.nr_resets);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(reset_starfive_jh71x0_register_with_info);
> diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h
> index db7d39a87f87..36f198139602 100644
> --- a/drivers/reset/starfive/reset-starfive-jh71x0.h
> +++ b/drivers/reset/starfive/reset-starfive-jh71x0.h
> @@ -6,9 +6,28 @@
> #ifndef __RESET_STARFIVE_JH71X0_H
> #define __RESET_STARFIVE_JH71X0_H
>
> +struct jh71x0_reset_map {
> + unsigned long reset_id;
> + unsigned long hw_id;
> +};
> +
> +struct jh71x0_reset_info {
> + unsigned int nr_resets;
> + unsigned int assert_offset;
> + unsigned int status_offset;
> + bool discontiguous;
This seems superfluous, (map != NULL) means discontiguous already.
> + const struct jh71x0_reset_map *map;
> +};
> +
regards
Philipp
next prev parent reply other threads:[~2026-11-12 11:21 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-08 12:33 [PATCH v6 00/15] Add basic clocks and resets for JHB100 SoC Changhuang Liang
2026-10-08 12:33 ` [PATCH v6 01/15] clk: starfive: jh7110-sys: Fix memory leak in reset controller register Changhuang Liang
2026-10-08 12:33 ` [PATCH v6 02/15] clk: starfive: jh71x0: Move reset controller registration to jh71x0 common code Changhuang Liang
2026-10-12 10:21 ` Jerome Brunet
2026-10-08 12:33 ` [PATCH v6 03/15] reset: starfive: jh7110: Match auxiliary device names to jh71x0 clk driver Changhuang Liang
2026-10-12 10:21 ` Jerome Brunet
2026-10-08 12:33 ` [PATCH v6 04/15] clk: starfive: jh71x0: Add generic CRG probe helper Changhuang Liang
2026-10-12 10:21 ` Jerome Brunet
2026-10-08 12:33 ` [PATCH v6 05/15] clk: starfive: Add JHB100 System-0 clock generator driver Changhuang Liang
2026-10-12 10:21 ` Jerome Brunet
2026-10-13 5:29 ` Changhuang Liang
2026-10-13 9:05 ` Jerome Brunet
2026-10-08 12:33 ` [PATCH v6 06/15] clk: starfive: Add JHB100 System-1 " Changhuang Liang
2026-10-12 10:21 ` Jerome Brunet
2026-10-08 12:33 ` [PATCH v6 07/15] clk: starfive: Add JHB100 System-2 " Changhuang Liang
2026-10-12 10:21 ` Jerome Brunet
2026-10-08 12:33 ` [PATCH v6 08/15] clk: starfive: Introduce idiv ops for inverted divider clocks Changhuang Liang
2026-10-12 10:21 ` Jerome Brunet
2026-10-14 3:16 ` Changhuang Liang
2026-10-17 14:22 ` Jerome Brunet
2026-10-08 12:33 ` [PATCH v6 09/15] clk: starfive: Expand the storage of clock parent index Changhuang Liang
2026-10-08 12:33 ` [PATCH v6 10/15] clk: starfive: Add StarFive JHB100 Peripheral-0 clock driver Changhuang Liang
2026-10-12 10:21 ` Jerome Brunet
2026-10-14 2:13 ` Changhuang Liang
2026-10-17 14:18 ` Jerome Brunet
2026-10-08 12:33 ` [PATCH v6 11/15] clk: starfive: Add StarFive JHB100 Peripheral-1 " Changhuang Liang
2026-10-08 12:33 ` [PATCH v6 12/15] clk: starfive: Add StarFive JHB100 Peripheral-2 " Changhuang Liang
2026-10-08 12:33 ` [PATCH v6 13/15] clk: starfive: Add StarFive JHB100 Peripheral-3 " Changhuang Liang
2026-10-08 12:33 ` [PATCH v6 14/15] reset: starfive: jh71x0: Support discontiguous reset IDs Changhuang Liang
2026-11-12 11:21 ` Philipp Zabel [this message]
2026-10-08 12:33 ` [PATCH v6 15/15] reset: starfive: Add StarFive JHB100 reset driver Changhuang Liang
2026-10-12 10:21 ` [PATCH v6 00/15] Add basic clocks and resets for JHB100 SoC Jerome Brunet
2026-10-12 19:03 ` Conor Dooley
2026-10-12 19:16 ` Jerome Brunet
2026-10-13 5:15 ` Changhuang Liang
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