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From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
	Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Cc: mkl@pengutronix.de, mani@kernel.org, thomas.kopp@microchip.com,
	mailhol@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, andersson@kernel.org,
	konradybcio@kernel.org, linux-can@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-msm@vger.kernel.org, mukesh.savaliya@oss.qualcomm.com,
	anup.kulkarni@oss.qualcomm.com
Subject: Re: [PATCH v1 2/2] arm64: dts: qcom: qcs6490-rb3gen2: Enable CAN bus controller
Date: Tue, 17 Feb 2026 12:15:12 +0100	[thread overview]
Message-ID: <465ab63f-3d0c-46f7-a08e-cdc5fc26b600@oss.qualcomm.com> (raw)
In-Reply-To: <2ho25tzct6t7gsuyufyg7m4a2ikmblhukb4uddwc7p35wd6yne@heippz3lh4kj>

On 2/4/26 2:09 AM, Dmitry Baryshkov wrote:
> On Tue, Feb 03, 2026 at 05:07:11PM +0530, Viken Dadhaniya wrote:
>>
>>
>> On 1/19/2026 11:59 AM, Dmitry Baryshkov wrote:
>>> On Mon, Jan 19, 2026 at 10:21:37AM +0530, Viken Dadhaniya wrote:
>>>>
>>>>
>>>> On 1/9/2026 7:35 PM, Dmitry Baryshkov wrote:
>>>>> On Fri, Jan 09, 2026 at 06:23:39PM +0530, Viken Dadhaniya wrote:
>>>>>>
>>>>>>
>>>>>> On 1/8/2026 7:33 PM, Dmitry Baryshkov wrote:
>>>>>>> On Thu, Jan 08, 2026 at 06:22:00PM +0530, Viken Dadhaniya wrote:
>>>>>>>> Enable the MCP2518FD CAN controller on the QCS6490 RB3 Gen2 platform.
>>>>>>>> The controller is connected via SPI3 and uses a 40 MHz oscillator.
>>>>>>>> A GPIO hog for GPIO0 is included to configure the CAN transceiver in
>>>>>>>> Normal mode during boot.
>>>>>>>
>>>>>>> The main question is: what is so different between RB3 Gen2 and previous
>>>>>>> RB boards which also incorporated this CAN controller? Are there any
>>>>>>> board differences or is it that nobody tested the CAN beforehand?
>>>>>>>
>>>>>>
>>>>>> The behavior is consistent across platforms, but I do not have details on
>>>>>> how other platforms were tested.
>>>>>>
>>>>>> On the RB3Gen2 board, communication with the PCAN interface requires the
>>>>>> CAN transceiver to be in normal mode. Since the GPIO-controller support
>>>>>> was recently integrated into the driver, I configured the transceiver using a
>>>>>> GPIO hog property. Without this configuration, the transceiver is not set
>>>>>> to normal mode, and CAN communication does not work.
>>>>>
>>>>> How do we verify the mode on a running system? I have the boards, but I
>>>>> don't have anything connected to them over the CAN bus.
>>>>>
>>>>> BTW: can you recommend any simple setup to actually test the CAN bus on
>>>>> those devices?
>>>>>
>>>>
>>>> I tested the CAN controller using the following commands:
>>>>
>>>> 1. Loopback Mode Testing (GPIO hog not required)
>>>>
>>>> ip link set can0 down
>>>> ip link set can0 type can bitrate 500000 loopback on
>>>> ip link set can0 up
>>>> cansend can0 12345678#1122334455667788_B
>>>> candump can0
>>>>
>>>> 2. Testing with External CAN FD Adapter (PCAN-USB FD)
>>>
>>> Thanks! It's price doesn't make it esily available, but it answers the
>>> most imporant question: by the USB CAN adapter.
>>>
>>> Did you add
>>>
>>>> A GPIO hog was required to configure the transceiver in normal mode.
>>>
>>> I'd phrase it differently: to pull the transceiver out of standby mode.
>>> By using the GPIO pin you make it always stay in the normal mode. It is
>>> fine, but it is not optimal. Instead a proper solution would be to use
>>> the MCP251XFD_REG_IOCON_XSTBYEN bit. Could you please instead implement
>>> support for setting that bit, based on the DT property.
>>
>> Thanks for the suggestion.
>>
>> I tested enabling IOCON.XSTBYEN, but on this hardware it doesn’t bring
>> the transceiver out of standby by itself. With only XSTBYEN set, the bus
>> remains inactive and no frames reach the CAN adapter. Clearing LAT0
>> (driving GPIO0 low) is required to put the transceiver into normal mode;
>> data transfer works only after LAT0 is cleared.
> 
> Why? It should be doing exactly what is required. Could you please check
> the voltage on the pin with the XSTBYEN bit set?

If I'm interpreting the datasheet correctly, XSTBYEN only muxes the pin
into its function and does *not* actually impact the operating mode,
which would match what Viken is observing

Konrad

  reply	other threads:[~2026-02-17 11:15 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-08 12:51 [PATCH v1 0/2] dt-bindings: CAN: MCP251XFD GPIO hog support and QCS6490 CAN enablement Viken Dadhaniya
2026-01-08 12:51 ` [PATCH v1 1/2] dt-bindings: can: microchip,mcp251xfd: allow gpio-hog child nodes Viken Dadhaniya
2026-01-09  8:49   ` Krzysztof Kozlowski
2026-01-08 12:52 ` [PATCH v1 2/2] arm64: dts: qcom: qcs6490-rb3gen2: Enable CAN bus controller Viken Dadhaniya
2026-01-08 14:03   ` Dmitry Baryshkov
2026-01-09 12:53     ` Viken Dadhaniya
2026-01-09 14:05       ` Dmitry Baryshkov
2026-01-13 14:51         ` Konrad Dybcio
2026-01-19  4:51         ` Viken Dadhaniya
2026-01-19  6:29           ` Dmitry Baryshkov
2026-02-03 11:37             ` Viken Dadhaniya
2026-02-04  1:09               ` Dmitry Baryshkov
2026-02-17 11:15                 ` Konrad Dybcio [this message]
2026-02-18  0:19                   ` Dmitry Baryshkov
2026-03-12  6:34                     ` Viken Dadhaniya
2026-03-12  7:51                       ` Marc Kleine-Budde
2026-03-13  3:11                       ` Dmitry Baryshkov
2026-01-08 16:46   ` Manivannan Sadhasivam
2026-01-09 12:55     ` Viken Dadhaniya
2026-01-09  8:52   ` Marc Kleine-Budde
2026-01-09 13:10     ` Viken Dadhaniya

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