[PATCH v1 1/2] memory: tegra: Squash tegra20-mc into common tegra-mc driver

[PATCH v1 1/2] memory: tegra: Squash tegra20-mc into common tegra-mc driver

[Dmitry Osipenko]

Tegra30+ has some minor differences in registers / bits layout compared
to Tegra20. Let's squash Tegra20 driver into the common tegra-mc driver
to reduce code a tad, this also will be useful for the upcoming Tegra's MC
reset API.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/memory/Kconfig         |  10 --
 drivers/memory/Makefile        |   1 -
 drivers/memory/tegra/Makefile  |   1 +
 drivers/memory/tegra/mc.c      | 184 +++++++++++++++++++----------
 drivers/memory/tegra/mc.h      |  10 ++
 drivers/memory/tegra/tegra20.c |  72 ++++++++++++
 drivers/memory/tegra20-mc.c    | 254 -----------------------------------------
 include/soc/tegra/mc.h         |   4 +-
 8 files changed, 211 insertions(+), 325 deletions(-)
 create mode 100644 drivers/memory/tegra/tegra20.c
 delete mode 100644 drivers/memory/tegra20-mc.c

diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 19a0e83f260d..8d731d6c3e54 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -104,16 +104,6 @@ config MVEBU_DEVBUS
 	  Armada 370 and Armada XP. This controller allows to handle flash
 	  devices such as NOR, NAND, SRAM, and FPGA.
 
-config TEGRA20_MC
-	bool "Tegra20 Memory Controller(MC) driver"
-	default y
-	depends on ARCH_TEGRA_2x_SOC
-	help
-	  This driver is for the Memory Controller(MC) module available
-	  in Tegra20 SoCs, mainly for a address translation fault
-	  analysis, especially for IOMMU/GART(Graphics Address
-	  Relocation Table) module.
-
 config FSL_CORENET_CF
 	tristate "Freescale CoreNet Error Reporting"
 	depends on FSL_SOC_BOOKE
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index 66f55240830e..a01ab3e22f94 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -16,7 +16,6 @@ obj-$(CONFIG_OMAP_GPMC)		+= omap-gpmc.o
 obj-$(CONFIG_FSL_CORENET_CF)	+= fsl-corenet-cf.o
 obj-$(CONFIG_FSL_IFC)		+= fsl_ifc.o
 obj-$(CONFIG_MVEBU_DEVBUS)	+= mvebu-devbus.o
-obj-$(CONFIG_TEGRA20_MC)	+= tegra20-mc.o
 obj-$(CONFIG_JZ4780_NEMC)	+= jz4780-nemc.o
 obj-$(CONFIG_MTK_SMI)		+= mtk-smi.o
 obj-$(CONFIG_DA8XX_DDRCTL)	+= da8xx-ddrctl.o
diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile
index b44e8627a5e0..581624938e6b 100644
--- a/drivers/memory/tegra/Makefile
+++ b/drivers/memory/tegra/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 tegra-mc-y := mc.o
 
+tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC)  += tegra20.o
 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC)  += tegra30.o
 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index a4803ac192bb..187a9005351b 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -27,6 +27,7 @@
 #define  MC_INT_INVALID_SMMU_PAGE (1 << 10)
 #define  MC_INT_ARBITRATION_EMEM (1 << 9)
 #define  MC_INT_SECURITY_VIOLATION (1 << 8)
+#define  MC_INT_INVALID_GART_PAGE (1 << 7)
 #define  MC_INT_DECERR_EMEM (1 << 6)
 
 #define MC_INTMASK 0x004
@@ -53,7 +54,14 @@
 #define MC_EMEM_ADR_CFG 0x54
 #define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
 
+#define MC_GART_ERROR_REQ		0x30
+#define MC_DECERR_EMEM_OTHERS_STATUS	0x58
+#define MC_SECURITY_VIOLATION_STATUS	0x74
+
 static const struct of_device_id tegra_mc_of_match[] = {
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+	{ .compatible = "nvidia,tegra20-mc", .data = &tegra20_mc_soc },
+#endif
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 	{ .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
 #endif
@@ -79,6 +87,9 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
 	unsigned int i;
 	u32 value;
 
+	if (mc->soc->tegra20)
+		return 0;
+
 	/* compute the number of MC clock cycles per tick */
 	tick = mc->tick * clk_get_rate(mc->clk);
 	do_div(tick, NSEC_PER_SEC);
@@ -229,6 +240,7 @@ static int tegra_mc_setup_timings(struct tegra_mc *mc)
 static const char *const status_names[32] = {
 	[ 1] = "External interrupt",
 	[ 6] = "EMEM address decode error",
+	[ 7] = "GART page fault",
 	[ 8] = "Security violation",
 	[ 9] = "EMEM arbitration error",
 	[10] = "Page fault",
@@ -257,78 +269,124 @@ static irqreturn_t tegra_mc_irq(int irq, void *data)
 
 	for_each_set_bit(bit, &status, 32) {
 		const char *error = status_names[bit] ?: "unknown";
-		const char *client = "unknown", *desc;
-		const char *direction, *secure;
+		const char *client = "unknown", *desc = "";
+		const char *direction = "read", *secure = "";
 		phys_addr_t addr = 0;
 		unsigned int i;
-		char perm[7];
+		char perm[7] = { 0 };
 		u8 id, type;
-		u32 value;
+		u32 value, reg;
 
-		value = mc_readl(mc, MC_ERR_STATUS);
+		if (mc->soc->tegra20) {
+			switch (bit) {
+			case 6:
+				reg = MC_DECERR_EMEM_OTHERS_STATUS;
+				value = mc_readl(mc, reg);
 
-#ifdef CONFIG_PHYS_ADDR_T_64BIT
-		if (mc->soc->num_address_bits > 32) {
-			addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) &
-				MC_ERR_STATUS_ADR_HI_MASK);
-			addr <<= 32;
-		}
-#endif
+				id = value & mc->soc->client_id_mask;
+				desc = error_names[2];
 
-		if (value & MC_ERR_STATUS_RW)
-			direction = "write";
-		else
-			direction = "read";
+				if (value & BIT(31))
+					direction = "write";
+				break;
 
-		if (value & MC_ERR_STATUS_SECURITY)
-			secure = "secure ";
-		else
-			secure = "";
+			case 7:
+				reg = MC_GART_ERROR_REQ;
+				value = mc_readl(mc, reg);
 
-		id = value & mc->soc->client_id_mask;
+				id = (value >> 1) & mc->soc->client_id_mask;
+				desc = error_names[2];
 
-		for (i = 0; i < mc->soc->num_clients; i++) {
-			if (mc->soc->clients[i].id == id) {
-				client = mc->soc->clients[i].name;
+				if (value & BIT(0))
+					direction = "write";
+				break;
+
+			case 8:
+				reg = MC_SECURITY_VIOLATION_STATUS;
+				value = mc_readl(mc, reg);
+
+				id = value & mc->soc->client_id_mask;
+				type = (value & BIT(30)) ? 4 : 3;
+				desc = error_names[type];
+				secure = "secure ";
+
+				if (value & BIT(31))
+					direction = "write";
+				break;
+
+			default:
+				reg = 0;
+				direction = "";
+				id = mc->soc->num_clients;
 				break;
 			}
-		}
 
-		type = (value & MC_ERR_STATUS_TYPE_MASK) >>
-		       MC_ERR_STATUS_TYPE_SHIFT;
-		desc = error_names[type];
+			if (id < mc->soc->num_clients)
+				client = mc->soc->clients[id].name;
 
-		switch (value & MC_ERR_STATUS_TYPE_MASK) {
-		case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE:
-			perm[0] = ' ';
-			perm[1] = '[';
+			if (reg)
+				addr = mc_readl(mc, reg + sizeof(u32));
+		} else {
+			value = mc_readl(mc, MC_ERR_STATUS);
 
-			if (value & MC_ERR_STATUS_READABLE)
-				perm[2] = 'R';
-			else
-				perm[2] = '-';
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
+			if (mc->soc->num_address_bits > 32) {
+				addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) &
+					MC_ERR_STATUS_ADR_HI_MASK);
+				addr <<= 32;
+			}
+#endif
+			if (value & MC_ERR_STATUS_RW)
+				direction = "write";
 
-			if (value & MC_ERR_STATUS_WRITABLE)
-				perm[3] = 'W';
-			else
-				perm[3] = '-';
+			if (value & MC_ERR_STATUS_SECURITY)
+				secure = "secure ";
 
-			if (value & MC_ERR_STATUS_NONSECURE)
-				perm[4] = '-';
-			else
-				perm[4] = 'S';
+			id = value & mc->soc->client_id_mask;
 
-			perm[5] = ']';
-			perm[6] = '\0';
-			break;
+			for (i = 0; i < mc->soc->num_clients; i++) {
+				if (mc->soc->clients[i].id == id) {
+					client = mc->soc->clients[i].name;
+					break;
+				}
+			}
 
-		default:
-			perm[0] = '\0';
-			break;
-		}
+			type = (value & MC_ERR_STATUS_TYPE_MASK) >>
+			       MC_ERR_STATUS_TYPE_SHIFT;
+			desc = error_names[type];
+
+			switch (value & MC_ERR_STATUS_TYPE_MASK) {
+			case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE:
+				perm[0] = ' ';
+				perm[1] = '[';
+
+				if (value & MC_ERR_STATUS_READABLE)
+					perm[2] = 'R';
+				else
+					perm[2] = '-';
+
+				if (value & MC_ERR_STATUS_WRITABLE)
+					perm[3] = 'W';
+				else
+					perm[3] = '-';
 
-		value = mc_readl(mc, MC_ERR_ADR);
-		addr |= value;
+				if (value & MC_ERR_STATUS_NONSECURE)
+					perm[4] = '-';
+				else
+					perm[4] = 'S';
+
+				perm[5] = ']';
+				perm[6] = '\0';
+				break;
+
+			default:
+				perm[0] = '\0';
+				break;
+			}
+
+			value = mc_readl(mc, MC_ERR_ADR);
+			addr |= value;
+		}
 
 		dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n",
 				    client, secure, direction, &addr, error,
@@ -369,11 +427,18 @@ static int tegra_mc_probe(struct platform_device *pdev)
 	if (IS_ERR(mc->regs))
 		return PTR_ERR(mc->regs);
 
-	mc->clk = devm_clk_get(&pdev->dev, "mc");
-	if (IS_ERR(mc->clk)) {
-		dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
-			PTR_ERR(mc->clk));
-		return PTR_ERR(mc->clk);
+	if (mc->soc->tegra20) {
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		mc->regs2 = devm_ioremap_resource(&pdev->dev, res);
+		if (IS_ERR(mc->regs2))
+			return PTR_ERR(mc->regs2);
+	} else {
+		mc->clk = devm_clk_get(&pdev->dev, "mc");
+		if (IS_ERR(mc->clk)) {
+			dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
+				PTR_ERR(mc->clk));
+			return PTR_ERR(mc->clk);
+		}
 	}
 
 	err = tegra_mc_setup_latency_allowance(mc);
@@ -416,7 +481,8 @@ static int tegra_mc_probe(struct platform_device *pdev)
 
 	value = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
 		MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
-		MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM;
+		MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM |
+		MC_INT_INVALID_GART_PAGE;
 
 	mc_writel(mc, value, MC_INTMASK);
 
diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h
index ddb16676c3af..1642fbea5ce3 100644
--- a/drivers/memory/tegra/mc.h
+++ b/drivers/memory/tegra/mc.h
@@ -16,15 +16,25 @@
 
 static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset)
 {
+	if (mc->soc->tegra20 && offset >= 0x24)
+		return readl(mc->regs2 + offset - 0x3c);
+
 	return readl(mc->regs + offset);
 }
 
 static inline void mc_writel(struct tegra_mc *mc, u32 value,
 			     unsigned long offset)
 {
+	if (mc->soc->tegra20 && offset >= 0x24)
+		return writel(value, mc->regs2 + offset - 0x3c);
+
 	writel(value, mc->regs + offset);
 }
 
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+extern const struct tegra_mc_soc tegra20_mc_soc;
+#endif
+
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 extern const struct tegra_mc_soc tegra30_mc_soc;
 #endif
diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c
new file mode 100644
index 000000000000..81a082bdba19
--- /dev/null
+++ b/drivers/memory/tegra/tegra20.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "mc.h"
+
+static const struct tegra_mc_client tegra20_mc_clients[] = {
+	{ .name = "display0a" },
+	{ .name = "display0ab" },
+	{ .name = "display0b" },
+	{ .name = "display0bb" },
+	{ .name = "display0c" },
+	{ .name = "display0cb" },
+	{ .name = "display1b" },
+	{ .name = "display1bb" },
+	{ .name = "eppup" },
+	{ .name = "g2pr" },
+	{ .name = "g2sr" },
+	{ .name = "mpeunifbr" },
+	{ .name = "viruv" },
+	{ .name = "avpcarm7r" },
+	{ .name = "displayhc" },
+	{ .name = "displayhcb" },
+	{ .name = "fdcdrd" },
+	{ .name = "g2dr" },
+	{ .name = "host1xdmar" },
+	{ .name = "host1xr" },
+	{ .name = "idxsrd" },
+	{ .name = "mpcorer" },
+	{ .name = "mpe_ipred" },
+	{ .name = "mpeamemrd" },
+	{ .name = "mpecsrd" },
+	{ .name = "ppcsahbdmar" },
+	{ .name = "ppcsahbslvr" },
+	{ .name = "texsrd" },
+	{ .name = "vdebsevr" },
+	{ .name = "vdember" },
+	{ .name = "vdemcer" },
+	{ .name = "vdetper" },
+	{ .name = "eppu" },
+	{ .name = "eppv" },
+	{ .name = "eppy" },
+	{ .name = "mpeunifbw" },
+	{ .name = "viwsb" },
+	{ .name = "viwu" },
+	{ .name = "viwv" },
+	{ .name = "viwy" },
+	{ .name = "g2dw" },
+	{ .name = "avpcarm7w" },
+	{ .name = "fdcdwr" },
+	{ .name = "host1xw" },
+	{ .name = "ispw" },
+	{ .name = "mpcorew" },
+	{ .name = "mpecswr" },
+	{ .name = "ppcsahbdmaw" },
+	{ .name = "ppcsahbslvw" },
+	{ .name = "vdebsevw" },
+	{ .name = "vdembew" },
+	{ .name = "vdetpmw" },
+};
+
+const struct tegra_mc_soc tegra20_mc_soc = {
+	.clients = tegra20_mc_clients,
+	.num_clients = ARRAY_SIZE(tegra20_mc_clients),
+	.num_address_bits = 32,
+	.client_id_mask = 0x3f,
+	.tegra20 = true,
+};
diff --git a/drivers/memory/tegra20-mc.c b/drivers/memory/tegra20-mc.c
deleted file mode 100644
index cc309a05289a..000000000000
--- a/drivers/memory/tegra20-mc.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- * Tegra20 Memory Controller
- *
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/ratelimit.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-
-#define DRV_NAME "tegra20-mc"
-
-#define MC_INTSTATUS			0x0
-#define MC_INTMASK			0x4
-
-#define MC_INT_ERR_SHIFT		6
-#define MC_INT_ERR_MASK			(0x1f << MC_INT_ERR_SHIFT)
-#define MC_INT_DECERR_EMEM		BIT(MC_INT_ERR_SHIFT)
-#define MC_INT_INVALID_GART_PAGE	BIT(MC_INT_ERR_SHIFT + 1)
-#define MC_INT_SECURITY_VIOLATION	BIT(MC_INT_ERR_SHIFT + 2)
-#define MC_INT_ARBITRATION_EMEM		BIT(MC_INT_ERR_SHIFT + 3)
-
-#define MC_GART_ERROR_REQ		0x30
-#define MC_DECERR_EMEM_OTHERS_STATUS	0x58
-#define MC_SECURITY_VIOLATION_STATUS	0x74
-
-#define SECURITY_VIOLATION_TYPE		BIT(30)	/* 0=TRUSTZONE, 1=CARVEOUT */
-
-#define MC_CLIENT_ID_MASK		0x3f
-
-#define NUM_MC_REG_BANKS		2
-
-struct tegra20_mc {
-	void __iomem *regs[NUM_MC_REG_BANKS];
-	struct device *dev;
-};
-
-static inline u32 mc_readl(struct tegra20_mc *mc, u32 offs)
-{
-	u32 val = 0;
-
-	if (offs < 0x24)
-		val = readl(mc->regs[0] + offs);
-	else if (offs < 0x400)
-		val = readl(mc->regs[1] + offs - 0x3c);
-
-	return val;
-}
-
-static inline void mc_writel(struct tegra20_mc *mc, u32 val, u32 offs)
-{
-	if (offs < 0x24)
-		writel(val, mc->regs[0] + offs);
-	else if (offs < 0x400)
-		writel(val, mc->regs[1] + offs - 0x3c);
-}
-
-static const char * const tegra20_mc_client[] = {
-	"cbr_display0a",
-	"cbr_display0ab",
-	"cbr_display0b",
-	"cbr_display0bb",
-	"cbr_display0c",
-	"cbr_display0cb",
-	"cbr_display1b",
-	"cbr_display1bb",
-	"cbr_eppup",
-	"cbr_g2pr",
-	"cbr_g2sr",
-	"cbr_mpeunifbr",
-	"cbr_viruv",
-	"csr_avpcarm7r",
-	"csr_displayhc",
-	"csr_displayhcb",
-	"csr_fdcdrd",
-	"csr_g2dr",
-	"csr_host1xdmar",
-	"csr_host1xr",
-	"csr_idxsrd",
-	"csr_mpcorer",
-	"csr_mpe_ipred",
-	"csr_mpeamemrd",
-	"csr_mpecsrd",
-	"csr_ppcsahbdmar",
-	"csr_ppcsahbslvr",
-	"csr_texsrd",
-	"csr_vdebsevr",
-	"csr_vdember",
-	"csr_vdemcer",
-	"csr_vdetper",
-	"cbw_eppu",
-	"cbw_eppv",
-	"cbw_eppy",
-	"cbw_mpeunifbw",
-	"cbw_viwsb",
-	"cbw_viwu",
-	"cbw_viwv",
-	"cbw_viwy",
-	"ccw_g2dw",
-	"csw_avpcarm7w",
-	"csw_fdcdwr",
-	"csw_host1xw",
-	"csw_ispw",
-	"csw_mpcorew",
-	"csw_mpecswr",
-	"csw_ppcsahbdmaw",
-	"csw_ppcsahbslvw",
-	"csw_vdebsevw",
-	"csw_vdembew",
-	"csw_vdetpmw",
-};
-
-static void tegra20_mc_decode(struct tegra20_mc *mc, int n)
-{
-	u32 addr, req;
-	const char *client = "Unknown";
-	int idx, cid;
-	const struct reg_info {
-		u32 offset;
-		u32 write_bit;	/* 0=READ, 1=WRITE */
-		int cid_shift;
-		char *message;
-	} reg[] = {
-		{
-			.offset = MC_DECERR_EMEM_OTHERS_STATUS,
-			.write_bit = 31,
-			.message = "MC_DECERR",
-		},
-		{
-			.offset	= MC_GART_ERROR_REQ,
-			.cid_shift = 1,
-			.message = "MC_GART_ERR",
-
-		},
-		{
-			.offset = MC_SECURITY_VIOLATION_STATUS,
-			.write_bit = 31,
-			.message = "MC_SECURITY_ERR",
-		},
-	};
-
-	idx = n - MC_INT_ERR_SHIFT;
-	if ((idx < 0) || (idx >= ARRAY_SIZE(reg))) {
-		dev_err_ratelimited(mc->dev, "Unknown interrupt status %08lx\n",
-				    BIT(n));
-		return;
-	}
-
-	req = mc_readl(mc, reg[idx].offset);
-	cid = (req >> reg[idx].cid_shift) & MC_CLIENT_ID_MASK;
-	if (cid < ARRAY_SIZE(tegra20_mc_client))
-		client = tegra20_mc_client[cid];
-
-	addr = mc_readl(mc, reg[idx].offset + sizeof(u32));
-
-	dev_err_ratelimited(mc->dev, "%s (0x%08x): 0x%08x %s (%s %s)\n",
-			   reg[idx].message, req, addr, client,
-			   (req & BIT(reg[idx].write_bit)) ? "write" : "read",
-			   (reg[idx].offset == MC_SECURITY_VIOLATION_STATUS) ?
-			   ((req & SECURITY_VIOLATION_TYPE) ?
-			    "carveout" : "trustzone") : "");
-}
-
-static const struct of_device_id tegra20_mc_of_match[] = {
-	{ .compatible = "nvidia,tegra20-mc", },
-	{},
-};
-
-static irqreturn_t tegra20_mc_isr(int irq, void *data)
-{
-	u32 stat, mask, bit;
-	struct tegra20_mc *mc = data;
-
-	stat = mc_readl(mc, MC_INTSTATUS);
-	mask = mc_readl(mc, MC_INTMASK);
-	mask &= stat;
-	if (!mask)
-		return IRQ_NONE;
-	while ((bit = ffs(mask)) != 0) {
-		tegra20_mc_decode(mc, bit - 1);
-		mask &= ~BIT(bit - 1);
-	}
-
-	mc_writel(mc, stat, MC_INTSTATUS);
-	return IRQ_HANDLED;
-}
-
-static int tegra20_mc_probe(struct platform_device *pdev)
-{
-	struct resource *irq;
-	struct tegra20_mc *mc;
-	int i, err;
-	u32 intmask;
-
-	mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
-	if (!mc)
-		return -ENOMEM;
-	mc->dev = &pdev->dev;
-
-	for (i = 0; i < ARRAY_SIZE(mc->regs); i++) {
-		struct resource *res;
-
-		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
-		mc->regs[i] = devm_ioremap_resource(&pdev->dev, res);
-		if (IS_ERR(mc->regs[i]))
-			return PTR_ERR(mc->regs[i]);
-	}
-
-	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-	if (!irq)
-		return -ENODEV;
-	err = devm_request_irq(&pdev->dev, irq->start, tegra20_mc_isr,
-			       IRQF_SHARED, dev_name(&pdev->dev), mc);
-	if (err)
-		return -ENODEV;
-
-	platform_set_drvdata(pdev, mc);
-
-	intmask = MC_INT_INVALID_GART_PAGE |
-		MC_INT_DECERR_EMEM | MC_INT_SECURITY_VIOLATION;
-	mc_writel(mc, intmask, MC_INTMASK);
-	return 0;
-}
-
-static struct platform_driver tegra20_mc_driver = {
-	.probe = tegra20_mc_probe,
-	.driver = {
-		.name = DRV_NAME,
-		.of_match_table = tegra20_mc_of_match,
-	},
-};
-module_platform_driver(tegra20_mc_driver);
-
-MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
-MODULE_DESCRIPTION("Tegra20 MC driver");
-MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
index 44202ff897fd..858904c09d7d 100644
--- a/include/soc/tegra/mc.h
+++ b/include/soc/tegra/mc.h
@@ -99,12 +99,14 @@ struct tegra_mc_soc {
 	u8 client_id_mask;
 
 	const struct tegra_smmu_soc *smmu;
+
+	bool tegra20;
 };
 
 struct tegra_mc {
 	struct device *dev;
 	struct tegra_smmu *smmu;
-	void __iomem *regs;
+	void __iomem *regs, *regs2;
 	struct clk *clk;
 	int irq;
 
-- 
2.15.1

[PATCH v1 2/2] memory: tegra: Introduce memory client hot reset API

[Dmitry Osipenko]

In order to reset busy HW properly, memory controller needs to be
involved, otherwise it possible to get corrupted memory if HW was reset
during DMA. Introduce memory client 'hot reset' API that will be used
for resetting busy HW. The primary users are memory clients related to
video (decoder/encoder/camera) and graphics (2d/3d).

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/memory/tegra/mc.c       | 172 ++++++++++++++++++++++++++++++++++++++++
 drivers/memory/tegra/tegra114.c |  25 ++++++
 drivers/memory/tegra/tegra124.c |  32 ++++++++
 drivers/memory/tegra/tegra20.c  |  23 ++++++
 drivers/memory/tegra/tegra210.c |  27 +++++++
 drivers/memory/tegra/tegra30.c  |  25 ++++++
 include/soc/tegra/mc.h          |  60 ++++++++++++++
 7 files changed, 364 insertions(+)

diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index 187a9005351b..510519028728 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -7,11 +7,13 @@
  */
 
 #include <linux/clk.h>
+#include <linux/delay.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
+#include <linux/reset.h>
 #include <linux/slab.h>
 #include <linux/sort.h>
 
@@ -81,6 +83,139 @@ static const struct of_device_id tegra_mc_of_match[] = {
 };
 MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
 
+static int terga_mc_flush_dma(struct tegra_mc *mc, unsigned int id)
+{
+	unsigned int hw_id = mc->soc->modules[id].hw_id;
+	u32 val, reg_poll = mc->soc->reg_client_flush_status;
+	int retries = 3;
+
+	/* block clients DMA requests */
+	if (mc->soc->tegra20) {
+		val = mc_readl(mc, mc->soc->reg_client_ctrl) & ~BIT(hw_id);
+		mc_writel(mc, val, mc->soc->reg_client_ctrl);
+	} else {
+		val = mc_readl(mc, mc->soc->reg_client_ctrl) | BIT(hw_id);
+		mc_writel(mc, val, mc->soc->reg_client_ctrl);
+	}
+
+	/* wait for completion of the outstanding DMA requests */
+	if (mc->soc->tegra20) {
+		while (mc_readl(mc, reg_poll + hw_id * sizeof(u32)) != 0) {
+			if (!retries--)
+				return -EBUSY;
+
+			usleep_range(1000, 2000);
+		}
+	} else {
+		while ((mc_readl(mc, reg_poll) & BIT(hw_id)) == 0) {
+			if (!retries--)
+				return -EBUSY;
+
+			usleep_range(1000, 2000);
+		}
+	}
+
+	return 0;
+}
+
+static int terga_mc_unblock_dma(struct tegra_mc *mc, unsigned int id)
+{
+	unsigned int hw_id = mc->soc->modules[id].hw_id;
+	u32 val;
+
+	if (mc->soc->tegra20) {
+		val = mc_readl(mc, mc->soc->reg_client_ctrl) | BIT(hw_id);
+		mc_writel(mc, val, mc->soc->reg_client_ctrl);
+	} else {
+		val = mc_readl(mc, mc->soc->reg_client_ctrl) & ~BIT(hw_id);
+		mc_writel(mc, val, mc->soc->reg_client_ctrl);
+	}
+
+	return 0;
+}
+
+static int terga_mc_hotreset_assert(struct tegra_mc *mc, unsigned int id)
+{
+	unsigned int hw_id = mc->soc->modules[id].hw_id;
+	u32 val;
+
+	if (mc->soc->tegra20) {
+		val = mc_readl(mc, mc->soc->reg_client_hotresetn) & ~BIT(hw_id);
+		mc_writel(mc, val, mc->soc->reg_client_hotresetn);
+	}
+
+	return 0;
+}
+
+static int terga_mc_hotreset_deassert(struct tegra_mc *mc, unsigned int id)
+{
+	unsigned int hw_id = mc->soc->modules[id].hw_id;
+	u32 val;
+
+	if (mc->soc->tegra20) {
+		val = mc_readl(mc, mc->soc->reg_client_hotresetn) | BIT(hw_id);
+		mc_writel(mc, val, mc->soc->reg_client_hotresetn);
+	}
+
+	return 0;
+}
+
+static int tegra_mc_hot_reset(struct tegra_mc *mc, unsigned int id,
+			      struct reset_control *rst)
+{
+	int err;
+
+	/*
+	 * Block clients DMA requests and wait for completion of the
+	 * outstanding requests.
+	 */
+	err = terga_mc_flush_dma(mc, id);
+	if (err) {
+		dev_err(mc->dev, "Failed to flush DMA: %d\n", err);
+		return err;
+	}
+
+	/* put in reset HW that corresponds to the memory client */
+	err = reset_control_assert(rst);
+	if (err) {
+		dev_err(mc->dev, "Failed to assert HW reset: %d\n", err);
+		return err;
+	}
+
+	/* clear the client requests sitting before arbitration */
+	err = terga_mc_hotreset_assert(mc, id);
+	if (err) {
+		dev_err(mc->dev, "Failed to hot reset client: %d\n", err);
+		return err;
+	}
+
+	/* make sure that reset is propagated */
+	usleep_range(4000, 6000);
+
+	/* take out client from hot reset */
+	err = terga_mc_hotreset_deassert(mc, id);
+	if (err) {
+		dev_err(mc->dev, "Failed to deassert hot reset: %d\n", err);
+		return err;
+	}
+
+	/* take out from reset corresponding clients HW */
+	err = reset_control_deassert(rst);
+	if (err) {
+		dev_err(mc->dev, "Failed to deassert HW reset: %d\n", err);
+		return err;
+	}
+
+	/* allow new DMA requests to proceed to arbitration */
+	err = terga_mc_unblock_dma(mc, id);
+	if (err) {
+		dev_err(mc->dev, "Failed to unblock client: %d\n", err);
+		return err;
+	}
+
+	return 0;
+}
+
 static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
 {
 	unsigned long long tick;
@@ -416,6 +551,7 @@ static int tegra_mc_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	platform_set_drvdata(pdev, mc);
+	mutex_init(&mc->lock);
 	mc->soc = match->data;
 	mc->dev = &pdev->dev;
 
@@ -499,6 +635,42 @@ static struct platform_driver tegra_mc_driver = {
 	.probe = tegra_mc_probe,
 };
 
+static int tegra_mc_match(struct device *dev, void *data)
+{
+	return of_match_node(tegra_mc_of_match, dev->of_node) != NULL;
+}
+
+static struct tegra_mc *tegra_mc_find_device(void)
+{
+	struct device *dev;
+
+	dev = driver_find_device(&tegra_mc_driver.driver, NULL, NULL,
+				 tegra_mc_match);
+	if (!dev)
+		return NULL;
+
+	return dev_get_drvdata(dev);
+}
+
+int tegra_memory_client_hotreset(unsigned int id, struct reset_control *rst)
+{
+	struct tegra_mc *mc;
+	int ret;
+
+	mc = tegra_mc_find_device();
+	if (!mc)
+		return -ENODEV;
+
+	if (id >= mc->soc->num_modules || !mc->soc->modules[id].valid)
+		return -EINVAL;
+
+	mutex_lock(&mc->lock);
+	ret = tegra_mc_hot_reset(mc, id, rst);
+	mutex_unlock(&mc->lock);
+
+	return ret;
+}
+
 static int tegra_mc_init(void)
 {
 	return platform_driver_register(&tegra_mc_driver);
diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra114.c
index ba8fff3d66a6..c90325bd0c75 100644
--- a/drivers/memory/tegra/tegra114.c
+++ b/drivers/memory/tegra/tegra114.c
@@ -923,6 +923,27 @@ static const struct tegra_smmu_soc tegra114_smmu_soc = {
 	.num_asids = 4,
 };
 
+static const struct tegra_mc_module tegra114_mc_modules[] = {
+	[TEGRA_MEMORY_CLIENT_AFI]	= { .hw_id =  0, .valid = true },
+	[TEGRA_MEMORY_CLIENT_AVP]	= { .hw_id =  1, .valid = true },
+	[TEGRA_MEMORY_CLIENT_DC]	= { .hw_id =  2, .valid = true },
+	[TEGRA_MEMORY_CLIENT_DCB]	= { .hw_id =  3, .valid = true },
+	[TEGRA_MEMORY_CLIENT_EPP]	= { .hw_id =  4, .valid = true },
+	[TEGRA_MEMORY_CLIENT_2D]	= { .hw_id =  5, .valid = true },
+	[TEGRA_MEMORY_CLIENT_HOST1X]	= { .hw_id =  6, .valid = true },
+	[TEGRA_MEMORY_CLIENT_HDA]	= { .hw_id =  7, .valid = true },
+	[TEGRA_MEMORY_CLIENT_ISP]	= { .hw_id =  8, .valid = true },
+	[TEGRA_MEMORY_CLIENT_MPCORE]	= { .hw_id =  9, .valid = true },
+	[TEGRA_MEMORY_CLIENT_MPCORELP]	= { .hw_id = 10, .valid = true },
+	[TEGRA_MEMORY_CLIENT_MPE]	= { .hw_id = 11, .valid = true },
+	[TEGRA_MEMORY_CLIENT_3D0]	= { .hw_id = 12, .valid = true },
+	[TEGRA_MEMORY_CLIENT_3D1]	= { .hw_id = 13, .valid = true },
+	[TEGRA_MEMORY_CLIENT_PPCS]	= { .hw_id = 14, .valid = true },
+	[TEGRA_MEMORY_CLIENT_SATA]	= { .hw_id = 15, .valid = true },
+	[TEGRA_MEMORY_CLIENT_VDE]	= { .hw_id = 16, .valid = true },
+	[TEGRA_MEMORY_CLIENT_VI]	= { .hw_id = 17, .valid = true },
+};
+
 const struct tegra_mc_soc tegra114_mc_soc = {
 	.clients = tegra114_mc_clients,
 	.num_clients = ARRAY_SIZE(tegra114_mc_clients),
@@ -930,4 +951,8 @@ const struct tegra_mc_soc tegra114_mc_soc = {
 	.atom_size = 32,
 	.client_id_mask = 0x7f,
 	.smmu = &tegra114_smmu_soc,
+	.modules = tegra114_mc_modules,
+	.num_modules = ARRAY_SIZE(tegra114_mc_modules),
+	.reg_client_ctrl = 0x200,
+	.reg_client_flush_status = 0x204,
 };
diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c
index 5a58e440f4a7..722251c365e9 100644
--- a/drivers/memory/tegra/tegra124.c
+++ b/drivers/memory/tegra/tegra124.c
@@ -999,6 +999,30 @@ static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
 	{ .name = "vi",        .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },
 };
 
+static const struct tegra_mc_module tegra124_mc_modules[] = {
+	[TEGRA_MEMORY_CLIENT_AFI]	= { .hw_id =  0, .valid = true },
+	[TEGRA_MEMORY_CLIENT_AVP]	= { .hw_id =  1, .valid = true },
+	[TEGRA_MEMORY_CLIENT_DC]	= { .hw_id =  2, .valid = true },
+	[TEGRA_MEMORY_CLIENT_DCB]	= { .hw_id =  3, .valid = true },
+	[TEGRA_MEMORY_CLIENT_HOST1X]	= { .hw_id =  6, .valid = true },
+	[TEGRA_MEMORY_CLIENT_HDA]	= { .hw_id =  7, .valid = true },
+	[TEGRA_MEMORY_CLIENT_ISP2]	= { .hw_id =  8, .valid = true },
+	[TEGRA_MEMORY_CLIENT_MPCORE]	= { .hw_id =  9, .valid = true },
+	[TEGRA_MEMORY_CLIENT_MPCORELP]	= { .hw_id = 10, .valid = true },
+	[TEGRA_MEMORY_CLIENT_MSENC]	= { .hw_id = 11, .valid = true },
+	[TEGRA_MEMORY_CLIENT_PPCS]	= { .hw_id = 14, .valid = true },
+	[TEGRA_MEMORY_CLIENT_SATA]	= { .hw_id = 15, .valid = true },
+	[TEGRA_MEMORY_CLIENT_VDE]	= { .hw_id = 16, .valid = true },
+	[TEGRA_MEMORY_CLIENT_VI]	= { .hw_id = 17, .valid = true },
+	[TEGRA_MEMORY_CLIENT_VIC]	= { .hw_id = 18, .valid = true },
+	[TEGRA_MEMORY_CLIENT_XUSB_HOST]	= { .hw_id = 19, .valid = true },
+	[TEGRA_MEMORY_CLIENT_XUSB_DEV]	= { .hw_id = 20, .valid = true },
+	[TEGRA_MEMORY_CLIENT_TSEC]	= { .hw_id = 22, .valid = true },
+	[TEGRA_MEMORY_CLIENT_SDMMC1]	= { .hw_id = 29, .valid = true },
+	[TEGRA_MEMORY_CLIENT_SDMMC2]	= { .hw_id = 30, .valid = true },
+	[TEGRA_MEMORY_CLIENT_SDMMC3]	= { .hw_id = 31, .valid = true },
+};
+
 #ifdef CONFIG_ARCH_TEGRA_124_SOC
 static const struct tegra_smmu_soc tegra124_smmu_soc = {
 	.clients = tegra124_mc_clients,
@@ -1020,6 +1044,10 @@ const struct tegra_mc_soc tegra124_mc_soc = {
 	.smmu = &tegra124_smmu_soc,
 	.emem_regs = tegra124_mc_emem_regs,
 	.num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
+	.modules = tegra124_mc_modules,
+	.num_modules = ARRAY_SIZE(tegra124_mc_modules),
+	.reg_client_ctrl = 0x200,
+	.reg_client_flush_status = 0x204,
 };
 #endif /* CONFIG_ARCH_TEGRA_124_SOC */
 
@@ -1042,5 +1070,9 @@ const struct tegra_mc_soc tegra132_mc_soc = {
 	.atom_size = 32,
 	.client_id_mask = 0x7f,
 	.smmu = &tegra132_smmu_soc,
+	.modules = tegra124_mc_modules,
+	.num_modules = ARRAY_SIZE(tegra124_mc_modules),
+	.reg_client_ctrl = 0x200,
+	.reg_client_flush_status = 0x204,
 };
 #endif /* CONFIG_ARCH_TEGRA_132_SOC */
diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c
index 81a082bdba19..4825013b948a 100644
--- a/drivers/memory/tegra/tegra20.c
+++ b/drivers/memory/tegra/tegra20.c
@@ -63,10 +63,33 @@ static const struct tegra_mc_client tegra20_mc_clients[] = {
 	{ .name = "vdetpmw" },
 };
 
+static const struct tegra_mc_module tegra20_mc_modules[] = {
+	[TEGRA_MEMORY_CLIENT_AVP]	= { .hw_id =  0, .valid = true },
+	[TEGRA_MEMORY_CLIENT_DC]	= { .hw_id =  1, .valid = true },
+	[TEGRA_MEMORY_CLIENT_DCB]	= { .hw_id =  2, .valid = true },
+	[TEGRA_MEMORY_CLIENT_EPP]	= { .hw_id =  3, .valid = true },
+	[TEGRA_MEMORY_CLIENT_2D]	= { .hw_id =  4, .valid = true },
+	[TEGRA_MEMORY_CLIENT_HOST1X]	= { .hw_id =  5, .valid = true },
+	[TEGRA_MEMORY_CLIENT_ISP]	= { .hw_id =  6, .valid = true },
+	[TEGRA_MEMORY_CLIENT_MPCORE]	= { .hw_id =  7, .valid = true },
+	[TEGRA_MEMORY_CLIENT_MPEA]	= { .hw_id =  8, .valid = true },
+	[TEGRA_MEMORY_CLIENT_MPEB]	= { .hw_id =  9, .valid = true },
+	[TEGRA_MEMORY_CLIENT_MPEC]	= { .hw_id = 10, .valid = true },
+	[TEGRA_MEMORY_CLIENT_3D]	= { .hw_id = 11, .valid = true },
+	[TEGRA_MEMORY_CLIENT_PPCS]	= { .hw_id = 12, .valid = true },
+	[TEGRA_MEMORY_CLIENT_VDE]	= { .hw_id = 13, .valid = true },
+	[TEGRA_MEMORY_CLIENT_VI]	= { .hw_id = 14, .valid = true },
+};
+
 const struct tegra_mc_soc tegra20_mc_soc = {
 	.clients = tegra20_mc_clients,
 	.num_clients = ARRAY_SIZE(tegra20_mc_clients),
 	.num_address_bits = 32,
 	.client_id_mask = 0x3f,
 	.tegra20 = true,
+	.modules = tegra20_mc_modules,
+	.num_modules = ARRAY_SIZE(tegra20_mc_modules),
+	.reg_client_ctrl = 0x100,
+	.reg_client_hotresetn = 0x104,
+	.reg_client_flush_status = 0x140,
 };
diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
index 5e144abe4c18..58f0b816cf0e 100644
--- a/drivers/memory/tegra/tegra210.c
+++ b/drivers/memory/tegra/tegra210.c
@@ -1059,6 +1059,29 @@ static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
 	{ .name = "tsecb",     .swgroup = TEGRA_SWGROUP_TSECB,     .reg = 0xad4 },
 };
 
+static const struct tegra_mc_module tegra210_mc_modules[] = {
+	[TEGRA_MEMORY_CLIENT_AFI]	= { .hw_id =  0, .valid = true },
+	[TEGRA_MEMORY_CLIENT_AVP]	= { .hw_id =  1, .valid = true },
+	[TEGRA_MEMORY_CLIENT_DC]	= { .hw_id =  2, .valid = true },
+	[TEGRA_MEMORY_CLIENT_DCB]	= { .hw_id =  3, .valid = true },
+	[TEGRA_MEMORY_CLIENT_HOST1X]	= { .hw_id =  6, .valid = true },
+	[TEGRA_MEMORY_CLIENT_HDA]	= { .hw_id =  7, .valid = true },
+	[TEGRA_MEMORY_CLIENT_ISP2]	= { .hw_id =  8, .valid = true },
+	[TEGRA_MEMORY_CLIENT_MPCORE]	= { .hw_id =  9, .valid = true },
+	[TEGRA_MEMORY_CLIENT_MPCORELP]	= { .hw_id = 10, .valid = true },
+	[TEGRA_MEMORY_CLIENT_NVENC]	= { .hw_id = 11, .valid = true },
+	[TEGRA_MEMORY_CLIENT_PPCS]	= { .hw_id = 14, .valid = true },
+	[TEGRA_MEMORY_CLIENT_SATA]	= { .hw_id = 15, .valid = true },
+	[TEGRA_MEMORY_CLIENT_VI]	= { .hw_id = 17, .valid = true },
+	[TEGRA_MEMORY_CLIENT_VIC]	= { .hw_id = 18, .valid = true },
+	[TEGRA_MEMORY_CLIENT_XUSB_HOST]	= { .hw_id = 19, .valid = true },
+	[TEGRA_MEMORY_CLIENT_XUSB_DEV]	= { .hw_id = 20, .valid = true },
+	[TEGRA_MEMORY_CLIENT_TSEC]	= { .hw_id = 22, .valid = true },
+	[TEGRA_MEMORY_CLIENT_SDMMC1]	= { .hw_id = 29, .valid = true },
+	[TEGRA_MEMORY_CLIENT_SDMMC2]	= { .hw_id = 30, .valid = true },
+	[TEGRA_MEMORY_CLIENT_SDMMC3]	= { .hw_id = 31, .valid = true },
+};
+
 static const struct tegra_smmu_soc tegra210_smmu_soc = {
 	.clients = tegra210_mc_clients,
 	.num_clients = ARRAY_SIZE(tegra210_mc_clients),
@@ -1077,4 +1100,8 @@ const struct tegra_mc_soc tegra210_mc_soc = {
 	.atom_size = 64,
 	.client_id_mask = 0xff,
 	.smmu = &tegra210_smmu_soc,
+	.modules = tegra210_mc_modules,
+	.num_modules = ARRAY_SIZE(tegra210_mc_modules),
+	.reg_client_ctrl = 0x200,
+	.reg_client_flush_status = 0x204,
 };
diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c
index b44737840e70..5a129919fa11 100644
--- a/drivers/memory/tegra/tegra30.c
+++ b/drivers/memory/tegra/tegra30.c
@@ -945,6 +945,27 @@ static const struct tegra_smmu_soc tegra30_smmu_soc = {
 	.num_asids = 4,
 };
 
+static const struct tegra_mc_module tegra30_mc_modules[] = {
+	[TEGRA_MEMORY_CLIENT_AFI]	= { .hw_id =  0, .valid = true },
+	[TEGRA_MEMORY_CLIENT_AVP]	= { .hw_id =  1, .valid = true },
+	[TEGRA_MEMORY_CLIENT_DC]	= { .hw_id =  2, .valid = true },
+	[TEGRA_MEMORY_CLIENT_DCB]	= { .hw_id =  3, .valid = true },
+	[TEGRA_MEMORY_CLIENT_EPP]	= { .hw_id =  4, .valid = true },
+	[TEGRA_MEMORY_CLIENT_2D]	= { .hw_id =  5, .valid = true },
+	[TEGRA_MEMORY_CLIENT_HOST1X]	= { .hw_id =  6, .valid = true },
+	[TEGRA_MEMORY_CLIENT_HDA]	= { .hw_id =  7, .valid = true },
+	[TEGRA_MEMORY_CLIENT_ISP]	= { .hw_id =  8, .valid = true },
+	[TEGRA_MEMORY_CLIENT_MPCORE]	= { .hw_id =  9, .valid = true },
+	[TEGRA_MEMORY_CLIENT_MPCORELP]	= { .hw_id = 10, .valid = true },
+	[TEGRA_MEMORY_CLIENT_MPE]	= { .hw_id = 11, .valid = true },
+	[TEGRA_MEMORY_CLIENT_3D0]	= { .hw_id = 12, .valid = true },
+	[TEGRA_MEMORY_CLIENT_3D1]	= { .hw_id = 13, .valid = true },
+	[TEGRA_MEMORY_CLIENT_PPCS]	= { .hw_id = 14, .valid = true },
+	[TEGRA_MEMORY_CLIENT_SATA]	= { .hw_id = 15, .valid = true },
+	[TEGRA_MEMORY_CLIENT_VDE]	= { .hw_id = 16, .valid = true },
+	[TEGRA_MEMORY_CLIENT_VI]	= { .hw_id = 17, .valid = true },
+};
+
 const struct tegra_mc_soc tegra30_mc_soc = {
 	.clients = tegra30_mc_clients,
 	.num_clients = ARRAY_SIZE(tegra30_mc_clients),
@@ -952,4 +973,8 @@ const struct tegra_mc_soc tegra30_mc_soc = {
 	.atom_size = 16,
 	.client_id_mask = 0x7f,
 	.smmu = &tegra30_smmu_soc,
+	.modules = tegra30_mc_modules,
+	.num_modules = ARRAY_SIZE(tegra30_mc_modules),
+	.reg_client_ctrl = 0x200,
+	.reg_client_flush_status = 0x204,
 };
diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
index 858904c09d7d..41ffccc43afc 100644
--- a/include/soc/tegra/mc.h
+++ b/include/soc/tegra/mc.h
@@ -9,11 +9,13 @@
 #ifndef __SOC_TEGRA_MC_H__
 #define __SOC_TEGRA_MC_H__
 
+#include <linux/mutex.h>
 #include <linux/types.h>
 
 struct clk;
 struct device;
 struct page;
+struct reset_control;
 
 struct tegra_smmu_enable {
 	unsigned int reg;
@@ -86,6 +88,11 @@ static inline void tegra_smmu_remove(struct tegra_smmu *smmu)
 }
 #endif
 
+struct tegra_mc_module {
+	unsigned int hw_id;
+	bool valid;
+};
+
 struct tegra_mc_soc {
 	const struct tegra_mc_client *clients;
 	unsigned int num_clients;
@@ -101,6 +108,13 @@ struct tegra_mc_soc {
 	const struct tegra_smmu_soc *smmu;
 
 	bool tegra20;
+
+	const struct tegra_mc_module *modules;
+	unsigned int num_modules;
+
+	u32 reg_client_ctrl;
+	u32 reg_client_hotresetn;
+	u32 reg_client_flush_status;
 };
 
 struct tegra_mc {
@@ -115,9 +129,55 @@ struct tegra_mc {
 
 	struct tegra_mc_timing *timings;
 	unsigned int num_timings;
+
+	struct mutex lock;
 };
 
 void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate);
 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc);
 
+#define TEGRA_MEMORY_CLIENT_AVP		0
+#define TEGRA_MEMORY_CLIENT_DC		1
+#define TEGRA_MEMORY_CLIENT_DCB		2
+#define TEGRA_MEMORY_CLIENT_EPP		3
+#define TEGRA_MEMORY_CLIENT_2D		4
+#define TEGRA_MEMORY_CLIENT_HOST1X	5
+#define TEGRA_MEMORY_CLIENT_ISP		6
+#define TEGRA_MEMORY_CLIENT_MPCORE	7
+#define TEGRA_MEMORY_CLIENT_MPCORELP	8
+#define TEGRA_MEMORY_CLIENT_MPEA	9
+#define TEGRA_MEMORY_CLIENT_MPEB	10
+#define TEGRA_MEMORY_CLIENT_MPEC	11
+#define TEGRA_MEMORY_CLIENT_3D		12
+#define TEGRA_MEMORY_CLIENT_3D1		13
+#define TEGRA_MEMORY_CLIENT_PPCS	14
+#define TEGRA_MEMORY_CLIENT_VDE		15
+#define TEGRA_MEMORY_CLIENT_VI		16
+#define TEGRA_MEMORY_CLIENT_AFI		17
+#define TEGRA_MEMORY_CLIENT_HDA		18
+#define TEGRA_MEMORY_CLIENT_SATA	19
+#define TEGRA_MEMORY_CLIENT_MSENC	20
+#define TEGRA_MEMORY_CLIENT_VIC		21
+#define TEGRA_MEMORY_CLIENT_XUSB_HOST	22
+#define TEGRA_MEMORY_CLIENT_XUSB_DEV	23
+#define TEGRA_MEMORY_CLIENT_TSEC	24
+#define TEGRA_MEMORY_CLIENT_SDMMC1	25
+#define TEGRA_MEMORY_CLIENT_SDMMC2	26
+#define TEGRA_MEMORY_CLIENT_SDMMC3	27
+#define TEGRA_MEMORY_CLIENT_MAX		TEGRA_MEMORY_CLIENT_SDMMC3
+
+#define TEGRA_MEMORY_CLIENT_3D0		TEGRA_MEMORY_CLIENT_3D
+#define TEGRA_MEMORY_CLIENT_MPE		TEGRA_MEMORY_CLIENT_MPEA
+#define TEGRA_MEMORY_CLIENT_NVENC	TEGRA_MEMORY_CLIENT_MSENC
+#define TEGRA_MEMORY_CLIENT_ISP2	TEGRA_MEMORY_CLIENT_ISP
+
+#ifdef CONFIG_ARCH_TEGRA
+int tegra_memory_client_hotreset(unsigned int id, struct reset_control *rst);
+#else
+int tegra_memory_client_hotreset(unsigned int id, struct reset_control *rst)
+{
+	return -ENOSYS;
+}
+#endif /* CONFIG_ARCH_TEGRA */
+
 #endif /* __SOC_TEGRA_MC_H__ */
-- 
2.15.1

Re: [PATCH v1 2/2] memory: tegra: Introduce memory client hot reset API

[Dmitry Osipenko]

On 13.12.2017 06:12, Dmitry Osipenko wrote:
> In order to reset busy HW properly, memory controller needs to be
> involved, otherwise it possible to get corrupted memory if HW was reset
> during DMA. Introduce memory client 'hot reset' API that will be used
> for resetting busy HW. The primary users are memory clients related to
> video (decoder/encoder/camera) and graphics (2d/3d).

I forgot to export symbol and realized that assert/deassert functions would be
necessary. For now I'll wait for the comments to v1.