memory barriers and MMIO, once again...

memory barriers and MMIO, once again...

[Stefan Richter]

Hi all,

in a single thread of execution, writel() and friends are ordered WRT
each other.  But I keep forgetting one thing:

Is writel() ordered WRT regular memory accesses?  That is, if I prepare
data in a coherent DMA buffer and then tell the device by writel() that
it's good to go, do I need a wmb() before the writel()?

*If* the answer to this is yes, then I also seem to need a wmb() between
dma_sync_single_for_device() and writel() if that writel tells the
device to use data from that synced DMA area, because the sync expands
to empty inline functions on simple architectures.  Or are there further
ordering guarantees on these architectures which eliminate the need for
a wmb() in this case?  If so, would I still need a barrier()?

Thanks,
-- 
Stefan Richter
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http://arcgraph.de/sr/