Re: [PATCH 2/2] phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap

[Roger Quadros <rogerq@kernel.org>]

On 13/12/2022 14:48, Sinthu Raja wrote:
> Serdes wiz supports both LN23 and LN10 Type-C swap. Add support to

SerDes?

what is wiz?

It has nothing to do with Type-C. It is just a lane swap.
There may or may not be a Type-C port.

> configure LN23 bit to swap between lane2 or lane3 if required.

What do you mean by "swap between lane2 or lane3"?

Do you mean "swap lanes 2 and 3"?

Is LN23 bit supported on all variants?

> 
> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
> ---
>  drivers/phy/ti/phy-j721e-wiz.c | 33 +++++++++++++++++++++++++++++----
>  1 file changed, 29 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
> index b17eec632d49..0091892af0b0 100644
> --- a/drivers/phy/ti/phy-j721e-wiz.c
> +++ b/drivers/phy/ti/phy-j721e-wiz.c
> @@ -58,6 +58,11 @@ enum wiz_lane_standard_mode {
>  	LANE_MODE_GEN4,
>  };
>  
> +enum wiz_lane_typec_swap_mode {
> +	LANE10_SWAP = 0,
> +	LANE23_SWAP = 2,
> +};

What is this? Is it a register setting?

> +
>  enum wiz_refclk_mux_sel {
>  	PLL0_REFCLK,
>  	PLL1_REFCLK,
> @@ -194,6 +199,9 @@ static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {
>  static const struct reg_field typec_ln10_swap =
>  					REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
>  
> +static const struct reg_field typec_ln23_swap =
> +					REG_FIELD(WIZ_SERDES_TYPEC, 31, 31);
> +
>  struct wiz_clk_mux {
>  	struct clk_hw		hw;
>  	struct regmap_field	*field;
> @@ -366,6 +374,7 @@ struct wiz {
>  	struct regmap_field	*mux_sel_field[WIZ_MUX_NUM_CLOCKS];
>  	struct regmap_field	*div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
>  	struct regmap_field	*typec_ln10_swap;
> +	struct regmap_field	*typec_ln23_swap;
>  	struct regmap_field	*sup_legacy_clk_override;
>  
>  	struct device		*dev;
> @@ -675,6 +684,13 @@ static int wiz_regfield_init(struct wiz *wiz)
>  		return PTR_ERR(wiz->typec_ln10_swap);
>  	}
>  
> +	wiz->typec_ln23_swap = devm_regmap_field_alloc(dev, regmap,
> +						       typec_ln23_swap);
> +	if (IS_ERR(wiz->typec_ln23_swap)) {
> +		dev_err(dev, "LN23_SWAP reg field init failed\n");
> +		return PTR_ERR(wiz->typec_ln23_swap);
> +	}
> +
>  	wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);
>  	if (IS_ERR(wiz->phy_en_refclk)) {
>  		dev_err(dev, "PHY_EN_REFCLK reg field init failed\n");
> @@ -1242,15 +1258,24 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
>  				regmap_field_write(wiz->typec_ln10_swap, 0);
>  		} else {
>  			/* if no typec-dir gpio was specified, and USB lines
> -			 * are connected to Lane 0 then set LN10 SWAP bit to 1.
> +			 * are connected to SWAP lanes '0' or '2' then set LN10 SWAP
> +			 * or LN23 bit to 1 respectively.
>  			 */
>  			u32 num_lanes = wiz->num_lanes;
>  			int i;
>  
>  			for (i = 0; i < num_lanes; i++) {
> -				if ((wiz->lane_phy_type[i] == PHY_TYPE_USB3) \
> -						&& wiz->lane_phy_reg[i] == 0) {
> -					regmap_field_write(wiz->typec_ln10_swap, 1);
> +				if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) {
> +					switch (wiz->lane_phy_reg[i]) {
> +					case LANE10_SWAP:
> +						regmap_field_write(wiz->typec_ln10_swap, 1);
> +						break;
> +					case LANE23_SWAP:
> +						regmap_field_write(wiz->typec_ln23_swap, 1);
> +						break;
> +					default:
> +						break;
> +					}

Could you please explain what is going on here?
What is the basis for deciding if LN10 or LN23 bit must be set or not?

What about clearing those bits?

>  				}
>  			}
>  		}

cheers,
-roger