From: Sinan Kaya <okaya@codeaurora.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: linux-pci@vger.kernel.org, timur@codeaurora.org,
alex.williamson@redhat.com, linux-arm-msm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Bjorn Helgaas <bhelgaas@google.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH V10 2/3] PCI: handle CRS returned by device after FLR
Date: Tue, 22 Aug 2017 23:21:24 -0400 [thread overview]
Message-ID: <48497e49-21c2-9289-f546-2b0ef938beb0@codeaurora.org> (raw)
In-Reply-To: <20170821180030.GB28977@bhelgaas-glaptop.roam.corp.google.com>
On 8/21/2017 2:00 PM, Bjorn Helgaas wrote:
> On Mon, Aug 21, 2017 at 09:44:09AM -0400, Sinan Kaya wrote:
>> Hi Bjorn,
>>
>> On 8/18/2017 5:01 PM, Bjorn Helgaas wrote:
>
> It would still be interesting to see the lspci output. Likely <MAbort
> in the upstream bridge will be set even before the FLR because of
> aborts during enumeration. The PCI core should probably clear that
> after enumeration. I expect that if you manually clear it with
> setpci, do the lspci, do the FLR, do another lspci, you will probably
> see <MAbort being set by this pci_flr_wait() loop. We might want to
> consider clearing it here as well.
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Interrupt: pin A routed to IRQ 345
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 00002000-00002fff
Memory behind bridge: 00100000-002fffff
Prefetchable memory behind bridge: 0000090400000000-00000904001fffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
FLR reset here with CRS to the NVMe drive.
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Interrupt: pin A routed to IRQ 345
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 00002000-00002fff
Memory behind bridge: 00100000-002fffff
Prefetchable memory behind bridge: 0000090400000000-00000904001fffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
I don't see <MAbort getting set.
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
next prev parent reply other threads:[~2017-08-23 3:21 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-11 16:56 [PATCH V10 1/3] PCI: introduce pci_bus_wait_crs() function Sinan Kaya
2017-08-11 16:56 ` [PATCH V10 2/3] PCI: handle CRS returned by device after FLR Sinan Kaya
2017-08-18 21:01 ` Bjorn Helgaas
2017-08-21 13:44 ` Sinan Kaya
2017-08-21 18:00 ` Bjorn Helgaas
2017-08-23 3:21 ` Sinan Kaya [this message]
2017-08-23 20:01 ` Bjorn Helgaas
2017-08-11 16:56 ` [PATCH V10 3/3] PCI: display not responding message while device is unreachable Sinan Kaya
2017-08-18 3:00 ` [PATCH V10 1/3] PCI: introduce pci_bus_wait_crs() function Bjorn Helgaas
2017-08-18 13:33 ` Sinan Kaya
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