* [PATCH V2 1/4] dt-bindings: phy: qcom,m31: Add IPQ5018 compatible
2023-08-30 11:17 [PATCH V2 0/4] Enable IPQ5018 USB2 support Nitheesh Sekar
@ 2023-08-30 11:17 ` Nitheesh Sekar
2023-08-30 11:17 ` [PATCH V2 2/4] phy: qcom-m31: Add compatible, phy init sequence for IPQ5018 Nitheesh Sekar
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Nitheesh Sekar @ 2023-08-30 11:17 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, conor+dt, gregkh, quic_srichara,
quic_varada, quic_wcheng, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-usb
Cc: Nitheesh Sekar
IPQ5332 qcom,m31 phy driver can support IPQ5018.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
---
.../devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml
index 2671a048c926..e77576d06c0e 100644
--- a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml
@@ -17,7 +17,9 @@ description:
properties:
compatible:
items:
- - const: qcom,ipq5332-usb-hsphy
+ - enum:
+ - qcom,ipq5018-usb-hsphy
+ - qcom,ipq5332-usb-hsphy
"#phy-cells":
const: 0
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH V2 2/4] phy: qcom-m31: Add compatible, phy init sequence for IPQ5018
2023-08-30 11:17 [PATCH V2 0/4] Enable IPQ5018 USB2 support Nitheesh Sekar
2023-08-30 11:17 ` [PATCH V2 1/4] dt-bindings: phy: qcom,m31: Add IPQ5018 compatible Nitheesh Sekar
@ 2023-08-30 11:17 ` Nitheesh Sekar
2023-08-30 12:37 ` Konrad Dybcio
2023-08-30 20:09 ` Dmitry Baryshkov
2023-08-30 11:17 ` [PATCH V2 3/4] arm64: dts: qcom: ipq5018: Add USB related nodes Nitheesh Sekar
2023-08-30 11:17 ` [PATCH V2 4/4] arm64: dts: qcom: ipq5018: Enable USB Nitheesh Sekar
3 siblings, 2 replies; 9+ messages in thread
From: Nitheesh Sekar @ 2023-08-30 11:17 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, conor+dt, gregkh, quic_srichara,
quic_varada, quic_wcheng, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-usb
Cc: Nitheesh Sekar
Add phy init sequence and compatible string for IPQ5018
chipset.
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
---
V2:
Updated the commit message.
---
drivers/phy/qualcomm/phy-qcom-m31.c | 60 +++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-m31.c b/drivers/phy/qualcomm/phy-qcom-m31.c
index ed08072ca032..81b72ebde305 100644
--- a/drivers/phy/qualcomm/phy-qcom-m31.c
+++ b/drivers/phy/qualcomm/phy-qcom-m31.c
@@ -82,6 +82,59 @@ struct m31_priv_data {
unsigned int nregs;
};
+struct m31_phy_regs m31_ipq5018_regs[] = {
+ {
+ USB_PHY_CFG0,
+ UTMI_PHY_OVERRIDE_EN,
+ 0
+ },
+ {
+ USB_PHY_UTMI_CTRL5,
+ POR_EN,
+ 15
+ },
+ {
+ USB_PHY_FSEL_SEL,
+ FREQ_SEL,
+ 0
+ },
+ {
+ USB_PHY_HS_PHY_CTRL_COMMON0,
+ COMMONONN | FSEL | RETENABLEN,
+ 0
+ },
+ {
+ USB_PHY_REFCLK_CTRL,
+ CLKCORE,
+ 0
+ },
+ {
+ USB_PHY_UTMI_CTRL5,
+ POR_EN,
+ 0
+ },
+ {
+ USB_PHY_HS_PHY_CTRL2,
+ USB2_SUSPEND_N_SEL | USB2_SUSPEND_N | USB2_UTMI_CLK_EN,
+ 0
+ },
+ {
+ USB_PHY_UTMI_CTRL5,
+ 0x0,
+ 0
+ },
+ {
+ USB_PHY_HS_PHY_CTRL2,
+ USB2_SUSPEND_N | USB2_UTMI_CLK_EN,
+ 0
+ },
+ {
+ USB_PHY_CFG0,
+ 0x0,
+ 0
+ },
+};
+
struct m31_phy_regs m31_ipq5332_regs[] = {
{
USB_PHY_CFG0,
@@ -268,6 +321,12 @@ static int m31usb_phy_probe(struct platform_device *pdev)
return PTR_ERR_OR_ZERO(phy_provider);
}
+static const struct m31_priv_data m31_ipq5018_data = {
+ .ulpi_mode = false,
+ .regs = m31_ipq5018_regs,
+ .nregs = ARRAY_SIZE(m31_ipq5018_regs),
+};
+
static const struct m31_priv_data m31_ipq5332_data = {
.ulpi_mode = false,
.regs = m31_ipq5332_regs,
@@ -275,6 +334,7 @@ static const struct m31_priv_data m31_ipq5332_data = {
};
static const struct of_device_id m31usb_phy_id_table[] = {
+ { .compatible = "qcom,ipq5018-usb-hsphy", .data = &m31_ipq5018_data },
{ .compatible = "qcom,ipq5332-usb-hsphy", .data = &m31_ipq5332_data },
{ },
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH V2 2/4] phy: qcom-m31: Add compatible, phy init sequence for IPQ5018
2023-08-30 11:17 ` [PATCH V2 2/4] phy: qcom-m31: Add compatible, phy init sequence for IPQ5018 Nitheesh Sekar
@ 2023-08-30 12:37 ` Konrad Dybcio
2023-08-30 20:09 ` Dmitry Baryshkov
1 sibling, 0 replies; 9+ messages in thread
From: Konrad Dybcio @ 2023-08-30 12:37 UTC (permalink / raw)
To: Nitheesh Sekar, agross, andersson, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, conor+dt, gregkh, quic_srichara,
quic_varada, quic_wcheng, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-usb
On 30.08.2023 13:17, Nitheesh Sekar wrote:
> Add phy init sequence and compatible string for IPQ5018
> chipset.
>
> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
> ---
> V2:
> Updated the commit message.
> ---
> drivers/phy/qualcomm/phy-qcom-m31.c | 60 +++++++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-m31.c b/drivers/phy/qualcomm/phy-qcom-m31.c
> index ed08072ca032..81b72ebde305 100644
> --- a/drivers/phy/qualcomm/phy-qcom-m31.c
> +++ b/drivers/phy/qualcomm/phy-qcom-m31.c
> @@ -82,6 +82,59 @@ struct m31_priv_data {
> unsigned int nregs;
> };
>
> +struct m31_phy_regs m31_ipq5018_regs[] = {
static const?
Konrad
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH V2 2/4] phy: qcom-m31: Add compatible, phy init sequence for IPQ5018
2023-08-30 11:17 ` [PATCH V2 2/4] phy: qcom-m31: Add compatible, phy init sequence for IPQ5018 Nitheesh Sekar
2023-08-30 12:37 ` Konrad Dybcio
@ 2023-08-30 20:09 ` Dmitry Baryshkov
1 sibling, 0 replies; 9+ messages in thread
From: Dmitry Baryshkov @ 2023-08-30 20:09 UTC (permalink / raw)
To: Nitheesh Sekar
Cc: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, conor+dt, gregkh, quic_srichara,
quic_varada, quic_wcheng, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-usb
On Wed, 30 Aug 2023 at 21:32, Nitheesh Sekar <quic_nsekar@quicinc.com> wrote:
>
> Add phy init sequence and compatible string for IPQ5018
> chipset.
>
> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
> ---
> V2:
> Updated the commit message.
> ---
> drivers/phy/qualcomm/phy-qcom-m31.c | 60 +++++++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-m31.c b/drivers/phy/qualcomm/phy-qcom-m31.c
> index ed08072ca032..81b72ebde305 100644
> --- a/drivers/phy/qualcomm/phy-qcom-m31.c
> +++ b/drivers/phy/qualcomm/phy-qcom-m31.c
> @@ -82,6 +82,59 @@ struct m31_priv_data {
> unsigned int nregs;
> };
>
> +struct m31_phy_regs m31_ipq5018_regs[] = {
> + {
> + USB_PHY_CFG0,
> + UTMI_PHY_OVERRIDE_EN,
> + 0
> + },
c99 initialisers? And maybe drop the 0 delay inits.
> + {
> + USB_PHY_UTMI_CTRL5,
> + POR_EN,
> + 15
> + },
> + {
> + USB_PHY_FSEL_SEL,
> + FREQ_SEL,
> + 0
> + },
> + {
> + USB_PHY_HS_PHY_CTRL_COMMON0,
> + COMMONONN | FSEL | RETENABLEN,
> + 0
> + },
> + {
> + USB_PHY_REFCLK_CTRL,
> + CLKCORE,
> + 0
> + },
> + {
> + USB_PHY_UTMI_CTRL5,
> + POR_EN,
> + 0
> + },
> + {
> + USB_PHY_HS_PHY_CTRL2,
> + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N | USB2_UTMI_CLK_EN,
> + 0
> + },
> + {
> + USB_PHY_UTMI_CTRL5,
> + 0x0,
> + 0
> + },
> + {
> + USB_PHY_HS_PHY_CTRL2,
> + USB2_SUSPEND_N | USB2_UTMI_CLK_EN,
> + 0
> + },
> + {
> + USB_PHY_CFG0,
> + 0x0,
> + 0
> + },
> +};
> +
> struct m31_phy_regs m31_ipq5332_regs[] = {
> {
> USB_PHY_CFG0,
> @@ -268,6 +321,12 @@ static int m31usb_phy_probe(struct platform_device *pdev)
> return PTR_ERR_OR_ZERO(phy_provider);
> }
>
> +static const struct m31_priv_data m31_ipq5018_data = {
> + .ulpi_mode = false,
> + .regs = m31_ipq5018_regs,
> + .nregs = ARRAY_SIZE(m31_ipq5018_regs),
> +};
> +
> static const struct m31_priv_data m31_ipq5332_data = {
> .ulpi_mode = false,
> .regs = m31_ipq5332_regs,
> @@ -275,6 +334,7 @@ static const struct m31_priv_data m31_ipq5332_data = {
> };
>
> static const struct of_device_id m31usb_phy_id_table[] = {
> + { .compatible = "qcom,ipq5018-usb-hsphy", .data = &m31_ipq5018_data },
> { .compatible = "qcom,ipq5332-usb-hsphy", .data = &m31_ipq5332_data },
> { },
> };
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH V2 3/4] arm64: dts: qcom: ipq5018: Add USB related nodes
2023-08-30 11:17 [PATCH V2 0/4] Enable IPQ5018 USB2 support Nitheesh Sekar
2023-08-30 11:17 ` [PATCH V2 1/4] dt-bindings: phy: qcom,m31: Add IPQ5018 compatible Nitheesh Sekar
2023-08-30 11:17 ` [PATCH V2 2/4] phy: qcom-m31: Add compatible, phy init sequence for IPQ5018 Nitheesh Sekar
@ 2023-08-30 11:17 ` Nitheesh Sekar
2023-08-30 19:43 ` Dmitry Baryshkov
2023-08-30 11:17 ` [PATCH V2 4/4] arm64: dts: qcom: ipq5018: Enable USB Nitheesh Sekar
3 siblings, 1 reply; 9+ messages in thread
From: Nitheesh Sekar @ 2023-08-30 11:17 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, conor+dt, gregkh, quic_srichara,
quic_varada, quic_wcheng, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-usb
Cc: Nitheesh Sekar, Amandeep Singh
Add USB phy and controller nodes.
Co-developed-by: Amandeep Singh <quic_amansing@quicinc.com>
Signed-off-by: Amandeep Singh <quic_amansing@quicinc.com>
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
---
V2:
Fix ordering of the USB related nodes and use
generic node names.
---
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 54 +++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 9f13d2dcdfd5..917e4a2d8e64 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -93,6 +93,19 @@
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
+ usbphy0: phy@5b000 {
+ compatible = "qcom,ipq5018-usb-hsphy";
+ reg = <0x0005b000 0x120>;
+
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
+
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5018-tlmm";
reg = <0x01000000 0x300000>;
@@ -155,6 +168,47 @@
status = "disabled";
};
+ usb: usb@8af8800 {
+ compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
+ reg = <0x08af8800 0x400>;
+
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq";
+
+ clocks = <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+ <&gcc GCC_USB0_SLEEP_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "core",
+ "iface",
+ "sleep",
+ "mock_utmi";
+
+ resets = <&gcc GCC_USB0_BCR>;
+
+ qcom,select-utmi-as-pipe-clk;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ status = "disabled";
+
+ usb2_0_dwc: usb@8a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x08a00000 0xe000>;
+ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "ref";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ phy-names = "usb2-phy";
+ phys = <&usbphy0>;
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH V2 3/4] arm64: dts: qcom: ipq5018: Add USB related nodes
2023-08-30 11:17 ` [PATCH V2 3/4] arm64: dts: qcom: ipq5018: Add USB related nodes Nitheesh Sekar
@ 2023-08-30 19:43 ` Dmitry Baryshkov
2023-08-31 3:10 ` Nitheesh Sekar
0 siblings, 1 reply; 9+ messages in thread
From: Dmitry Baryshkov @ 2023-08-30 19:43 UTC (permalink / raw)
To: Nitheesh Sekar
Cc: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, conor+dt, gregkh, quic_srichara,
quic_varada, quic_wcheng, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-usb, Amandeep Singh
On Wed, 30 Aug 2023 at 21:30, Nitheesh Sekar <quic_nsekar@quicinc.com> wrote:
>
> Add USB phy and controller nodes.
>
> Co-developed-by: Amandeep Singh <quic_amansing@quicinc.com>
> Signed-off-by: Amandeep Singh <quic_amansing@quicinc.com>
> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
> ---
> V2:
> Fix ordering of the USB related nodes and use
> generic node names.
> ---
> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 54 +++++++++++++++++++++++++++
> 1 file changed, 54 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index 9f13d2dcdfd5..917e4a2d8e64 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -93,6 +93,19 @@
> #size-cells = <1>;
> ranges = <0 0 0 0xffffffff>;
>
> + usbphy0: phy@5b000 {
> + compatible = "qcom,ipq5018-usb-hsphy";
> + reg = <0x0005b000 0x120>;
> +
> + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
> +
> + resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> tlmm: pinctrl@1000000 {
> compatible = "qcom,ipq5018-tlmm";
> reg = <0x01000000 0x300000>;
> @@ -155,6 +168,47 @@
> status = "disabled";
> };
>
> + usb: usb@8af8800 {
> + compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
> + reg = <0x08af8800 0x400>;
> +
> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hs_phy_irq";
> +
> + clocks = <&gcc GCC_USB0_MASTER_CLK>,
> + <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
> + <&gcc GCC_USB0_SLEEP_CLK>,
> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> + clock-names = "core",
> + "iface",
> + "sleep",
> + "mock_utmi";
> +
> + resets = <&gcc GCC_USB0_BCR>;
> +
> + qcom,select-utmi-as-pipe-clk;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + status = "disabled";
> +
> + usb2_0_dwc: usb@8a00000 {
As we have seen from the next patchset, this host supports USB 3.0.
Can you please drop the 2_0 part of the label?
> + compatible = "snps,dwc3";
> + reg = <0x08a00000 0xe000>;
> + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> + clock-names = "ref";
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> + phy-names = "usb2-phy";
> + phys = <&usbphy0>;
> + tx-fifo-resize;
> + snps,is-utmi-l1-suspend;
> + snps,hird-threshold = /bits/ 8 <0x0>;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_u3_susphy_quirk;
> + };
> + };
> +
> intc: interrupt-controller@b000000 {
> compatible = "qcom,msm-qgic2";
> reg = <0x0b000000 0x1000>, /* GICD */
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH V2 3/4] arm64: dts: qcom: ipq5018: Add USB related nodes
2023-08-30 19:43 ` Dmitry Baryshkov
@ 2023-08-31 3:10 ` Nitheesh Sekar
0 siblings, 0 replies; 9+ messages in thread
From: Nitheesh Sekar @ 2023-08-31 3:10 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, conor+dt, gregkh, quic_srichara,
quic_varada, quic_wcheng, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-usb, Amandeep Singh
On 8/31/2023 1:13 AM, Dmitry Baryshkov wrote:
> On Wed, 30 Aug 2023 at 21:30, Nitheesh Sekar <quic_nsekar@quicinc.com> wrote:
>> Add USB phy and controller nodes.
>>
>> Co-developed-by: Amandeep Singh <quic_amansing@quicinc.com>
>> Signed-off-by: Amandeep Singh <quic_amansing@quicinc.com>
>> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
>> ---
>> V2:
>> Fix ordering of the USB related nodes and use
>> generic node names.
>> ---
>> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 54 +++++++++++++++++++++++++++
>> 1 file changed, 54 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> index 9f13d2dcdfd5..917e4a2d8e64 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> @@ -93,6 +93,19 @@
>> #size-cells = <1>;
>> ranges = <0 0 0 0xffffffff>;
>>
>> + usbphy0: phy@5b000 {
>> + compatible = "qcom,ipq5018-usb-hsphy";
>> + reg = <0x0005b000 0x120>;
>> +
>> + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
>> +
>> + resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
>> +
>> + #phy-cells = <0>;
>> +
>> + status = "disabled";
>> + };
>> +
>> tlmm: pinctrl@1000000 {
>> compatible = "qcom,ipq5018-tlmm";
>> reg = <0x01000000 0x300000>;
>> @@ -155,6 +168,47 @@
>> status = "disabled";
>> };
>>
>> + usb: usb@8af8800 {
>> + compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
>> + reg = <0x08af8800 0x400>;
>> +
>> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "hs_phy_irq";
>> +
>> + clocks = <&gcc GCC_USB0_MASTER_CLK>,
>> + <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
>> + <&gcc GCC_USB0_SLEEP_CLK>,
>> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>> + clock-names = "core",
>> + "iface",
>> + "sleep",
>> + "mock_utmi";
>> +
>> + resets = <&gcc GCC_USB0_BCR>;
>> +
>> + qcom,select-utmi-as-pipe-clk;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + status = "disabled";
>> +
>> + usb2_0_dwc: usb@8a00000 {
> As we have seen from the next patchset, this host supports USB 3.0.
> Can you please drop the 2_0 part of the label?
Sure. Will drop "2_0".
Regards,
Nitheesh
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH V2 4/4] arm64: dts: qcom: ipq5018: Enable USB
2023-08-30 11:17 [PATCH V2 0/4] Enable IPQ5018 USB2 support Nitheesh Sekar
` (2 preceding siblings ...)
2023-08-30 11:17 ` [PATCH V2 3/4] arm64: dts: qcom: ipq5018: Add USB related nodes Nitheesh Sekar
@ 2023-08-30 11:17 ` Nitheesh Sekar
3 siblings, 0 replies; 9+ messages in thread
From: Nitheesh Sekar @ 2023-08-30 11:17 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, conor+dt, gregkh, quic_srichara,
quic_varada, quic_wcheng, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-usb
Cc: Nitheesh Sekar, Amandeep Singh
Enable USB2 in host mode.
Co-developed-by: Amandeep Singh <quic_amansing@quicinc.com>
Signed-off-by: Amandeep Singh <quic_amansing@quicinc.com>
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
---
V2:
Sort and reorder USB related nodes.
---
arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
index e636a1cb9b77..3eb3a98e3e12 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
@@ -67,6 +67,18 @@
};
};
+&usbphy0 {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb2_0_dwc {
+ dr_mode = "host";
+};
+
&xo_board_clk {
clock-frequency = <24000000>;
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 9+ messages in thread