[PATCH v3 0/6] Add minimal Exynos8855 SoC support

[PATCH v3 0/6] Add minimal Exynos8855 SoC support

[Alim Akhtar]

This series adds initial support for the Exynos8855 SoC and also
initial SMDK board support. 

Exynos8855 is octa-core CPUs, a combination of Cortex-A720 and Cortex-A520,
arranged in 3 clusters. And other peripheral for mobile application.

This initial support consists of CPUs, pinctrl and related nodes
needed for initial kernel boot.

With these patches, kernel can boot using initramfs till file system mounts.

More platform support will be added in near future, clock driver to go next.

Changes since v2:
* Addressed review comments from Peter Griffin and Krzysztof.
* Updated uses of GS101 MACROS for pinctrl driver
* Documented  wakeup interrupt binding
* Rebased on latest Linux-next
 
Chanegs since v1:
* Fixed some of the review comments by Sashiko [1]
* Dropped serial node, will be added once clock support is available
* Dropped wkup interrupt for CMGP block, will be added later

Link of v2:
https://lore.kernel.org/all/20260615085252.1964423-1-alim.akhtar@samsung.com/

Link of v1:
https://lore.kernel.org/linux-samsung-soc/20260612163020.411761-1-alim.akhtar@samsung.com/

[1] https://sashiko.dev/#/patchset/20260612163020.411761-1-alim.akhtar@samsung.com?part=4


Alim Akhtar (6):
  dt-binding: ARM: samsung: Add Samsung Exynos8855
  dt-binding: pinctrl: samsung: Add exynos8855-pinctrl compatible
  pinctrl: samsung: Add Exynos8855 pinctrl configuration
  dt-bindings: pinctrl: samsung: Add exynos8855-wakeup-eint compatible
  arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk
  MAINTAINERS: Add entry for Samsung Exynos8855 SoC

 .../bindings/arm/samsung/samsung-boards.yaml  |   6 +
 .../samsung,pinctrl-wakeup-interrupt.yaml     |   1 +
 .../bindings/pinctrl/samsung,pinctrl.yaml     |   1 +
 MAINTAINERS                                   |   7 +
 arch/arm64/boot/dts/exynos/Makefile           |   1 +
 .../boot/dts/exynos/exynos8855-pinctrl.dtsi   | 574 ++++++++++++++++++
 .../arm64/boot/dts/exynos/exynos8855-smdk.dts |  32 +
 arch/arm64/boot/dts/exynos/exynos8855.dtsi    | 204 +++++++
 .../pinctrl/samsung/pinctrl-exynos-arm64.c    | 132 ++++
 drivers/pinctrl/samsung/pinctrl-samsung.c     |   2 +
 drivers/pinctrl/samsung/pinctrl-samsung.h     |   1 +
 11 files changed, 961 insertions(+)
 create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
 create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
 create mode 100644 arch/arm64/boot/dts/exynos/exynos8855.dtsi


base-commit: 3d5670d672ae08b8c534b7beed6f57c8b44e7b43
-- 
2.34.1

[PATCH v3 1/6] dt-binding: ARM: samsung: Add Samsung Exynos8855

[Alim Akhtar]

Add Samsung Exynos8855 smdk board to documentation

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 .../devicetree/bindings/arm/samsung/samsung-boards.yaml     | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
index 753b3ba1b607..273464400477 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
@@ -235,6 +235,12 @@ properties:
               - winlink,e850-96                 # WinLink E850-96
           - const: samsung,exynos850
 
+      - description: Exynos8855 based boards
+        items:
+          - enum:
+              - samsung,exynos8855-smdk         # Samsung SMDK
+          - const: samsung,exynos8855
+
       - description: Exynos8895 based boards
         items:
           - enum:
-- 
2.34.1

Re: [PATCH v3 1/6] dt-binding: ARM: samsung: Add Samsung Exynos8855

[Ivaylo Ivanov]

On 6/27/26 20:12, Alim Akhtar wrote:
> Add Samsung Exynos8855 smdk board to documentation
> 
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  .../devicetree/bindings/arm/samsung/samsung-boards.yaml     | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> index 753b3ba1b607..273464400477 100644
> --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> @@ -235,6 +235,12 @@ properties:
>                - winlink,e850-96                 # WinLink E850-96
>            - const: samsung,exynos850
>  
> +      - description: Exynos8855 based boards
> +        items:
> +          - enum:
> +              - samsung,exynos8855-smdk         # Samsung SMDK
> +          - const: samsung,exynos8855

Is there any particular reason for using "exynos8855" rather than the commercial
name - exynos1580? We've already established using the latter naming scheme as a
convention (e.g. exynos3830 -> exynos850, exynos9830 -> exynos990) rather than
the development model numbers, so I don't think breaking that will help anyone
with the already painful model number confusion.

Best regards,
Ivaylo

> +
>        - description: Exynos8895 based boards
>          items:
>            - enum:

RE: [PATCH v3 1/6] dt-binding: ARM: samsung: Add Samsung Exynos8855

[Alim Akhtar]

Hi Ivaylo,
Thanks for your review. 

> -----Original Message-----
> From: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
> Sent: Monday, July 6, 2026 4:11 AM
> To: Alim Akhtar <alim.akhtar@samsung.com>; krzk@kernel.org;
> peter.griffin@linaro.org; robh@kernel.org; conor+dt@kernel.org;
> linusw@kernel.org
> Cc: linux-samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; linux-gpio@vger.kernel.org;
> hajun.sung@samsung.com
> Subject: Re: [PATCH v3 1/6] dt-binding: ARM: samsung: Add Samsung
> Exynos8855
> 
> On 6/27/26 20:12, Alim Akhtar wrote:
> > Add Samsung Exynos8855 smdk board to documentation
> >
> > Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> > ---
> >  .../devicetree/bindings/arm/samsung/samsung-boards.yaml     | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> > b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> > index 753b3ba1b607..273464400477 100644
> > ---
> > a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> > +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-
> boards.yam
> > +++ l
> > @@ -235,6 +235,12 @@ properties:
> >                - winlink,e850-96                 # WinLink E850-96
> >            - const: samsung,exynos850
> >
> > +      - description: Exynos8855 based boards
> > +        items:
> > +          - enum:
> > +              - samsung,exynos8855-smdk         # Samsung SMDK
> > +          - const: samsung,exynos8855
> 
> Is there any particular reason for using "exynos8855" rather than the
> commercial name - exynos1580? We've already established using the latter
> naming scheme as a convention (e.g. exynos3830 -> exynos850, exynos9830 ->
> exynos990) rather than the development model numbers, so I don't think
> breaking that will help anyone with the already painful model number confusion.
> 
The reason for using Exynos8855 is that it comes from the chip-id register, which is RO register.
And in my opinion it has to be chip-id, maintaining two names is confusing (as you also mentioned).
Yes, there were couple of deviation but let's come back to the "original" convention (which is to use chip-id).

@ Krzysztof, Peter 
Any input on this? 

> Best regards,
> Ivaylo
> 
> > +
> >        - description: Exynos8895 based boards
> >          items:
> >            - enum:

Re: [PATCH v3 1/6] dt-binding: ARM: samsung: Add Samsung Exynos8855

[Ivaylo Ivanov]

On 7/6/26 6:44 AM, Alim Akhtar wrote:
> Hi Ivaylo,
> Thanks for your review. 

No problem :D

> 
>> -----Original Message-----
>> From: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
>> Sent: Monday, July 6, 2026 4:11 AM
>> To: Alim Akhtar <alim.akhtar@samsung.com>; krzk@kernel.org;
>> peter.griffin@linaro.org; robh@kernel.org; conor+dt@kernel.org;
>> linusw@kernel.org
>> Cc: linux-samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org;
>> devicetree@vger.kernel.org; linux-gpio@vger.kernel.org;
>> hajun.sung@samsung.com
>> Subject: Re: [PATCH v3 1/6] dt-binding: ARM: samsung: Add Samsung
>> Exynos8855
>>
>> On 6/27/26 20:12, Alim Akhtar wrote:
>>> Add Samsung Exynos8855 smdk board to documentation
>>>
>>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>>> ---
>>>  .../devicetree/bindings/arm/samsung/samsung-boards.yaml     | 6 ++++++
>>>  1 file changed, 6 insertions(+)
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
>>> b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
>>> index 753b3ba1b607..273464400477 100644
>>> ---
>>> a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-
>> boards.yam
>>> +++ l
>>> @@ -235,6 +235,12 @@ properties:
>>>                - winlink,e850-96                 # WinLink E850-96
>>>            - const: samsung,exynos850
>>>
>>> +      - description: Exynos8855 based boards
>>> +        items:
>>> +          - enum:
>>> +              - samsung,exynos8855-smdk         # Samsung SMDK
>>> +          - const: samsung,exynos8855
>>
>> Is there any particular reason for using "exynos8855" rather than the
>> commercial name - exynos1580? We've already established using the latter
>> naming scheme as a convention (e.g. exynos3830 -> exynos850, exynos9830 ->
>> exynos990) rather than the development model numbers, so I don't think
>> breaking that will help anyone with the already painful model number confusion.
>>
> The reason for using Exynos8855 is that it comes from the chip-id register, which is RO register.
> And in my opinion it has to be chip-id, maintaining two names is confusing (as you also mentioned).

I see your point but I'm not sure whether exynos-based platforms like tensors
will follow this. Afaik GS101's development name is e9845. So there likely will
still be some deviation.

It's not really a fatal thing, just a nit imo because all bindings will have
to follow that for the upstreamed SoC, so non-revertable. But if maintainers
are okay with this, I'm happy to start using chip-id names for future contributions
too.

Best regards,
Ivaylo

> Yes, there were couple of deviation but let's come back to the "original" convention (which is to use chip-id).
> 
> @ Krzysztof, Peter 
> Any input on this? 
> 
>> Best regards,
>> Ivaylo
>>
>>> +
>>>        - description: Exynos8895 based boards
>>>          items:
>>>            - enum:
> 
> 

RE: [PATCH v3 1/6] dt-binding: ARM: samsung: Add Samsung Exynos8855

[Alim Akhtar]

> -----Original Message-----
> From: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
> Sent: Monday, July 6, 2026 1:27 PM
> To: Alim Akhtar <alim.akhtar@samsung.com>; krzk@kernel.org;
> peter.griffin@linaro.org; robh@kernel.org; conor+dt@kernel.org;
> linusw@kernel.org
> Cc: linux-samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; linux-gpio@vger.kernel.org;
> hajun.sung@samsung.com
> Subject: Re: [PATCH v3 1/6] dt-binding: ARM: samsung: Add Samsung
> Exynos8855
> 
> On 7/6/26 6:44 AM, Alim Akhtar wrote:
> > Hi Ivaylo,
> > Thanks for your review.
> 
> No problem :D
> 
> >
> >> -----Original Message-----
> >> From: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
> >> Sent: Monday, July 6, 2026 4:11 AM
> >> To: Alim Akhtar <alim.akhtar@samsung.com>; krzk@kernel.org;
> >> peter.griffin@linaro.org; robh@kernel.org; conor+dt@kernel.org;
> >> linusw@kernel.org
> >> Cc: linux-samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org;
> >> devicetree@vger.kernel.org; linux-gpio@vger.kernel.org;
> >> hajun.sung@samsung.com
> >> Subject: Re: [PATCH v3 1/6] dt-binding: ARM: samsung: Add Samsung
> >> Exynos8855
> >>
> >> On 6/27/26 20:12, Alim Akhtar wrote:
> >>> Add Samsung Exynos8855 smdk board to documentation
> >>>
> >>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> >>> ---
> >>>  .../devicetree/bindings/arm/samsung/samsung-boards.yaml     | 6 ++++++
> >>>  1 file changed, 6 insertions(+)
> >>>
> >>> diff --git
> >>> a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> >>> b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> >>> index 753b3ba1b607..273464400477 100644
> >>> ---
> >>> a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> >>> +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-
> >> boards.yam
> >>> +++ l
> >>> @@ -235,6 +235,12 @@ properties:
> >>>                - winlink,e850-96                 # WinLink E850-96
> >>>            - const: samsung,exynos850
> >>>
> >>> +      - description: Exynos8855 based boards
> >>> +        items:
> >>> +          - enum:
> >>> +              - samsung,exynos8855-smdk         # Samsung SMDK
> >>> +          - const: samsung,exynos8855
> >>
> >> Is there any particular reason for using "exynos8855" rather than the
> >> commercial name - exynos1580? We've already established using the
> >> latter naming scheme as a convention (e.g. exynos3830 -> exynos850,
> >> exynos9830 ->
> >> exynos990) rather than the development model numbers, so I don't
> >> think breaking that will help anyone with the already painful model number
> confusion.
> >>
> > The reason for using Exynos8855 is that it comes from the chip-id register,
> which is RO register.
> > And in my opinion it has to be chip-id, maintaining two names is confusing (as
> you also mentioned).
> 
> I see your point but I'm not sure whether exynos-based platforms like tensors
> will follow this. Afaik GS101's development name is e9845. So there likely will
> still be some deviation.
> 
Hmm...I would say, those are custom SoCs (of course based on Exynos as base platform) and they don’t carry "Exynos"
in their nomenclature, like GS101, or Artpec and many more... 
However Exynos8855 and other SoCs in this family are native Exynos SoCs.
So for Exynos SoCs (exception 850, 990), let's have chip-id based nomenclature as a standard, that's what I am thinking, it is easy to maintain that way. 

> It's not really a fatal thing, just a nit imo because all bindings will have to follow
> that for the upstreamed SoC, so non-revertable. But if maintainers are okay with
> this, I'm happy to start using chip-id names for future contributions too.
> 
Thank you, Looking forward for more contributions, no need to revert what is merged already. 

> Best regards,
> Ivaylo
> 
> > Yes, there were couple of deviation but let's come back to the "original"
> convention (which is to use chip-id).
> >
> > @ Krzysztof, Peter
> > Any input on this?
> >
> >> Best regards,
> >> Ivaylo
> >>
> >>> +
> >>>        - description: Exynos8895 based boards
> >>>          items:
> >>>            - enum:
> >
> >

Re: [PATCH v3 1/6] dt-binding: ARM: samsung: Add Samsung Exynos8855

[Krzysztof Kozlowski]

On 06/07/2026 05:44, Alim Akhtar wrote:
> Hi Ivaylo,
> Thanks for your review. 
> 
>> -----Original Message-----
>> From: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
>> Sent: Monday, July 6, 2026 4:11 AM
>> To: Alim Akhtar <alim.akhtar@samsung.com>; krzk@kernel.org;
>> peter.griffin@linaro.org; robh@kernel.org; conor+dt@kernel.org;
>> linusw@kernel.org
>> Cc: linux-samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org;
>> devicetree@vger.kernel.org; linux-gpio@vger.kernel.org;
>> hajun.sung@samsung.com
>> Subject: Re: [PATCH v3 1/6] dt-binding: ARM: samsung: Add Samsung
>> Exynos8855
>>
>> On 6/27/26 20:12, Alim Akhtar wrote:
>>> Add Samsung Exynos8855 smdk board to documentation
>>>
>>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>>> ---
>>>  .../devicetree/bindings/arm/samsung/samsung-boards.yaml     | 6 ++++++
>>>  1 file changed, 6 insertions(+)
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
>>> b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
>>> index 753b3ba1b607..273464400477 100644
>>> ---
>>> a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-
>> boards.yam
>>> +++ l
>>> @@ -235,6 +235,12 @@ properties:
>>>                - winlink,e850-96                 # WinLink E850-96
>>>            - const: samsung,exynos850
>>>
>>> +      - description: Exynos8855 based boards
>>> +        items:
>>> +          - enum:
>>> +              - samsung,exynos8855-smdk         # Samsung SMDK
>>> +          - const: samsung,exynos8855
>>
>> Is there any particular reason for using "exynos8855" rather than the
>> commercial name - exynos1580? We've already established using the latter
>> naming scheme as a convention (e.g. exynos3830 -> exynos850, exynos9830 ->
>> exynos990) rather than the development model numbers, so I don't think
>> breaking that will help anyone with the already painful model number confusion.
>>
> The reason for using Exynos8855 is that it comes from the chip-id register, which is RO register.
> And in my opinion it has to be chip-id, maintaining two names is confusing (as you also mentioned).
> Yes, there were couple of deviation but let's come back to the "original" convention (which is to use chip-id).
> 
> @ Krzysztof, Peter 
> Any input on this? 

Back in Exynos850 upstreaming, my preference was the chipid value, but I
agreed for marketing name. Marketing names are tricky, because:
1. They change,
2. They might multiply (two or three marketing names for the same die -
common case in Qualcomm),

That's why for Samsung SoCs, I rather prefer chipid value. For
Google/Axis/Tesla the case is different and we should use their naming -
some engineering name for example.



Best regards,
Krzysztof

Re: [PATCH v3 1/6] dt-binding: ARM: samsung: Add Samsung Exynos8855

[Peter Griffin]

Hi Alim / Ivaylo / Krysztof

On Mon, 6 Jul 2026 at 17:05, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 06/07/2026 05:44, Alim Akhtar wrote:
> > Hi Ivaylo,
> > Thanks for your review.
> >
> >> -----Original Message-----
> >> From: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
> >> Sent: Monday, July 6, 2026 4:11 AM
> >> To: Alim Akhtar <alim.akhtar@samsung.com>; krzk@kernel.org;
> >> peter.griffin@linaro.org; robh@kernel.org; conor+dt@kernel.org;
> >> linusw@kernel.org
> >> Cc: linux-samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org;
> >> devicetree@vger.kernel.org; linux-gpio@vger.kernel.org;
> >> hajun.sung@samsung.com
> >> Subject: Re: [PATCH v3 1/6] dt-binding: ARM: samsung: Add Samsung
> >> Exynos8855
> >>
> >> On 6/27/26 20:12, Alim Akhtar wrote:
> >>> Add Samsung Exynos8855 smdk board to documentation
> >>>
> >>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> >>> ---
> >>>  .../devicetree/bindings/arm/samsung/samsung-boards.yaml     | 6 ++++++
> >>>  1 file changed, 6 insertions(+)
> >>>
> >>> diff --git
> >>> a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> >>> b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> >>> index 753b3ba1b607..273464400477 100644
> >>> ---
> >>> a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> >>> +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-
> >> boards.yam
> >>> +++ l
> >>> @@ -235,6 +235,12 @@ properties:
> >>>                - winlink,e850-96                 # WinLink E850-96
> >>>            - const: samsung,exynos850
> >>>
> >>> +      - description: Exynos8855 based boards
> >>> +        items:
> >>> +          - enum:
> >>> +              - samsung,exynos8855-smdk         # Samsung SMDK
> >>> +          - const: samsung,exynos8855
> >>
> >> Is there any particular reason for using "exynos8855" rather than the
> >> commercial name - exynos1580? We've already established using the latter
> >> naming scheme as a convention (e.g. exynos3830 -> exynos850, exynos9830 ->
> >> exynos990) rather than the development model numbers, so I don't think
> >> breaking that will help anyone with the already painful model number confusion.
> >>
> > The reason for using Exynos8855 is that it comes from the chip-id register, which is RO register.
> > And in my opinion it has to be chip-id, maintaining two names is confusing (as you also mentioned).
> > Yes, there were couple of deviation but let's come back to the "original" convention (which is to use chip-id).
> >
> > @ Krzysztof, Peter
> > Any input on this?
>
> Back in Exynos850 upstreaming, my preference was the chipid value, but I
> agreed for marketing name. Marketing names are tricky, because:
> 1. They change,
> 2. They might multiply (two or three marketing names for the same die -
> common case in Qualcomm),
>
> That's why for Samsung SoCs, I rather prefer chipid value. For
> Google/Axis/Tesla the case is different and we should use their naming -
> some engineering name for example.

Using the chip ID value for Samsung Exynos SoCs and an engineering
name for ASICs sounds like a good approach to me.

For gs101 I also tried to document the various names in
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/arm/google.yaml.

Peter

Re: [PATCH v3 1/6] dt-binding: ARM: samsung: Add Samsung Exynos8855

[Peter Griffin]

On Sat, 27 Jun 2026 at 17:54, Alim Akhtar <alim.akhtar@samsung.com> wrote:
>
> Add Samsung Exynos8855 smdk board to documentation
>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---

Reviewed-by: Peter Griffin <peter.griffin@linaro.org>

>  .../devicetree/bindings/arm/samsung/samsung-boards.yaml     | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> index 753b3ba1b607..273464400477 100644
> --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> @@ -235,6 +235,12 @@ properties:
>                - winlink,e850-96                 # WinLink E850-96
>            - const: samsung,exynos850
>
> +      - description: Exynos8855 based boards
> +        items:
> +          - enum:
> +              - samsung,exynos8855-smdk         # Samsung SMDK
> +          - const: samsung,exynos8855
> +
>        - description: Exynos8895 based boards
>          items:
>            - enum:
> --
> 2.34.1
>

[PATCH v3 2/6] dt-binding: pinctrl: samsung: Add exynos8855-pinctrl compatible

[Alim Akhtar]

Document pin controller support on Exynos8855 SoC.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
index 7b006009ca0e..c4773701c92e 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
@@ -53,6 +53,7 @@ properties:
       - samsung,exynos7870-pinctrl
       - samsung,exynos7885-pinctrl
       - samsung,exynos850-pinctrl
+      - samsung,exynos8855-pinctrl
       - samsung,exynos8890-pinctrl
       - samsung,exynos8895-pinctrl
       - samsung,exynos9610-pinctrl
-- 
2.34.1

Re: [PATCH v3 2/6] dt-binding: pinctrl: samsung: Add exynos8855-pinctrl compatible

[Peter Griffin]

On Sat, 27 Jun 2026 at 17:54, Alim Akhtar <alim.akhtar@samsung.com> wrote:
>
> Document pin controller support on Exynos8855 SoC.
>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---

Reviewed-by: Peter Griffin <peter.griffin@linaro.org>

>  Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
> index 7b006009ca0e..c4773701c92e 100644
> --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
> @@ -53,6 +53,7 @@ properties:
>        - samsung,exynos7870-pinctrl
>        - samsung,exynos7885-pinctrl
>        - samsung,exynos850-pinctrl
> +      - samsung,exynos8855-pinctrl
>        - samsung,exynos8890-pinctrl
>        - samsung,exynos8895-pinctrl
>        - samsung,exynos9610-pinctrl
> --
> 2.34.1
>

[PATCH v3 3/6] pinctrl: samsung: Add Exynos8855 pinctrl configuration

[Alim Akhtar]

Add pinctrl configuration for Exynos8855. The bank type
macros are reused from EXYNOS850 and GS101 SoC.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 .../pinctrl/samsung/pinctrl-exynos-arm64.c    | 132 ++++++++++++++++++
 drivers/pinctrl/samsung/pinctrl-samsung.c     |   2 +
 drivers/pinctrl/samsung/pinctrl-samsung.h     |   1 +
 3 files changed, 135 insertions(+)

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index fe9f92cb037e..1aa977d2a1f8 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -943,6 +943,138 @@ const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = {
 	.num_ctrl	= ARRAY_SIZE(exynos850_pin_ctrl),
 };
 
+/* pin banks of exynos8855 pin-controller 0 (ALIVE) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks0[] __initconst = {
+	GS101_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00, 0x00),
+	GS101_PIN_BANK_EINTW(4, 0x020, "gpa1", 0x04, 0x08),
+	EXYNOS850_PIN_BANK_EINTN(3, 0x040, "gpq0"),
+	EXYNOS850_PIN_BANK_EINTN(2, 0x060, "gpq1"),
+	GS101_PIN_BANK_EINTW(1, 0x080, "gpc0", 0x08, 0x10),
+	GS101_PIN_BANK_EINTW(1, 0x0a0, "gpc1", 0x0c, 0x14),
+	GS101_PIN_BANK_EINTW(1, 0x0c0, "gpc2", 0x10, 0x18),
+	GS101_PIN_BANK_EINTW(1, 0x0e0, "gpc3", 0x14, 0x1c),
+	GS101_PIN_BANK_EINTW(1, 0x100, "gpc4", 0x18, 0x20),
+	GS101_PIN_BANK_EINTW(1, 0x120, "gpc5", 0x1c, 0x24),
+	GS101_PIN_BANK_EINTW(1, 0x140, "gpc6", 0x20, 0x28),
+	GS101_PIN_BANK_EINTW(1, 0x160, "gpc7", 0x24, 0x2c),
+	GS101_PIN_BANK_EINTW(1, 0x180, "gpc8", 0x28, 0x30),
+	GS101_PIN_BANK_EINTW(1, 0x1a0, "gpc9", 0x2c, 0x34),
+	GS101_PIN_BANK_EINTW(1, 0x1c0, "gpc10", 0x30, 0x38),
+	GS101_PIN_BANK_EINTW(1, 0x1e0, "gpc11", 0x34, 0x3c),
+	GS101_PIN_BANK_EINTW(1, 0x200, "gpc12", 0x38, 0x40),
+	GS101_PIN_BANK_EINTW(1, 0x220, "gpc13", 0x3c, 0x44),
+	GS101_PIN_BANK_EINTW(1, 0x240, "gpc14", 0x40, 0x48),
+	GS101_PIN_BANK_EINTW(1, 0x260, "gpj0", 0x44, 0x4c),
+	GS101_PIN_BANK_EINTW(1, 0x280, "gpj1", 0x48, 0x50),
+	GS101_PIN_BANK_EINTW(1, 0x2a0, "gpj2", 0x4c, 0x54),
+};
+
+/* pin banks of exynos8855 pin-controller 1 (CMGP) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks1[] __initconst = {
+	GS101_PIN_BANK_EINTW(1, 0x00,  "gpm0",  0x00, 0x00),
+	GS101_PIN_BANK_EINTW(1, 0x20,  "gpm1",  0x04, 0x04),
+	GS101_PIN_BANK_EINTW(1, 0x40,  "gpm2",  0x08, 0x08),
+	GS101_PIN_BANK_EINTW(1, 0x60,  "gpm3",  0x0c, 0x0c),
+	GS101_PIN_BANK_EINTW(1, 0x80,  "gpm4",  0x10, 0x10),
+	GS101_PIN_BANK_EINTW(1, 0xa0,  "gpm5",  0x14, 0x14),
+	GS101_PIN_BANK_EINTW(1, 0xc0,  "gpm6",  0x18, 0x18),
+	GS101_PIN_BANK_EINTW(1, 0xe0,  "gpm7",  0x1c, 0x1c),
+	GS101_PIN_BANK_EINTW(1, 0x100, "gpm8",  0x20, 0x20),
+	GS101_PIN_BANK_EINTW(1, 0x120, "gpm9",  0x24, 0x24),
+	GS101_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x28, 0x28),
+	GS101_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x2c, 0x2c),
+	GS101_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x30, 0x30),
+	GS101_PIN_BANK_EINTW(1, 0x1a0, "gpm13", 0x34, 0x34),
+	GS101_PIN_BANK_EINTW(1, 0x1c0, "gpm14", 0x38, 0x38),
+	GS101_PIN_BANK_EINTW(1, 0x1e0, "gpm15", 0x3c, 0x3c),
+	GS101_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40, 0x40),
+	GS101_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44, 0x44),
+	GS101_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x48, 0x48),
+	GS101_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x4c, 0x4c),
+	GS101_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x50, 0x50),
+	GS101_PIN_BANK_EINTW(1, 0x2a0, "gpm21", 0x54, 0x54),
+};
+
+/* pin banks of exynos8855 pin-controller 2 (HSI UFS) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks2[] __initconst = {
+	GS101_PIN_BANK_EINTG(2, 0x0, "gpf3", 0x00, 0x00),
+};
+
+/* pin banks of exynos8855 pin-controller 3 (PERIC) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks3[] __initconst = {
+	GS101_PIN_BANK_EINTG(8, 0x0,   "gpp0", 0x00, 0x00),
+	GS101_PIN_BANK_EINTG(8, 0x20,  "gpp1", 0x04, 0x08),
+	GS101_PIN_BANK_EINTG(6, 0x40,  "gpp2", 0x08, 0x10),
+	GS101_PIN_BANK_EINTG(4, 0x60,  "gpg0", 0x0c, 0x18),
+	GS101_PIN_BANK_EINTG(3, 0x80,  "gpg1", 0x10, 0x1c),
+	GS101_PIN_BANK_EINTG(6, 0xa0,  "gpb0", 0x14, 0x20),
+	GS101_PIN_BANK_EINTG(4, 0xc0,  "gpb1", 0x18, 0x28),
+};
+
+/* pin banks of exynos8855 pin-controller 4 (PERICMMC) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks4[] __initconst = {
+	GS101_PIN_BANK_EINTG(7, 0x0, "gpf2", 0x00, 0x00),
+};
+
+/* pin banks of exynos8855 pin-controller 5 (USI) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks5[] __initconst = {
+	GS101_PIN_BANK_EINTG(8, 0x00, "gpp3", 0x00, 0x00),
+	GS101_PIN_BANK_EINTG(2, 0x20, "gpp4", 0x04, 0x08),
+	GS101_PIN_BANK_EINTG(2, 0x40, "gpg2", 0x08, 0x0c),
+	GS101_PIN_BANK_EINTG(1, 0x60, "gpg3", 0x0c, 0x10),
+};
+
+static const struct samsung_pin_ctrl exynos8855_pin_ctrl[] __initconst = {
+	{
+		/* pin-controller instance 0 ALIVE data */
+		.pin_banks	= exynos8855_pin_banks0,
+		.nr_banks	= ARRAY_SIZE(exynos8855_pin_banks0),
+		.eint_wkup_init = exynos_eint_wkup_init,
+		.suspend	= gs101_pinctrl_suspend,
+		.resume		= gs101_pinctrl_resume,
+	}, {
+		/* pin-controller instance 1 CMGP data */
+		.pin_banks	= exynos8855_pin_banks1,
+		.nr_banks	= ARRAY_SIZE(exynos8855_pin_banks1),
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= gs101_pinctrl_suspend,
+		.resume		= gs101_pinctrl_resume,
+	}, {
+		/* pin-controller instance 2 HSI UFS data */
+		.pin_banks	= exynos8855_pin_banks2,
+		.nr_banks	= ARRAY_SIZE(exynos8855_pin_banks2),
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= gs101_pinctrl_suspend,
+		.resume		= gs101_pinctrl_resume,
+	}, {
+		/* pin-controller instance 3 PERIC data */
+		.pin_banks	= exynos8855_pin_banks3,
+		.nr_banks	= ARRAY_SIZE(exynos8855_pin_banks3),
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= gs101_pinctrl_suspend,
+		.resume		= gs101_pinctrl_resume,
+	}, {
+		/* pin-controller instance 4 PERICMMC data */
+		.pin_banks	= exynos8855_pin_banks4,
+		.nr_banks	= ARRAY_SIZE(exynos8855_pin_banks4),
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= gs101_pinctrl_suspend,
+		.resume		= gs101_pinctrl_resume,
+	}, {
+		/* pin-controller instance 5 USI data */
+		.pin_banks	= exynos8855_pin_banks5,
+		.nr_banks	= ARRAY_SIZE(exynos8855_pin_banks5),
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= gs101_pinctrl_suspend,
+		.resume		= gs101_pinctrl_resume,
+	},
+};
+
+const struct samsung_pinctrl_of_match_data exynos8855_of_data __initconst = {
+	.ctrl		= exynos8855_pin_ctrl,
+	.num_ctrl	= ARRAY_SIZE(exynos8855_pin_ctrl),
+};
+
 /* pin banks of exynos990 pin-controller 0 (ALIVE) */
 static struct samsung_pin_bank_data exynos990_pin_banks0[] = {
 	/* Must start with EINTG banks, ordered by EINT group number. */
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 5ac6f6b02327..5ecc9ed4c44d 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1500,6 +1500,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
 		.data = &exynos7885_of_data },
 	{ .compatible = "samsung,exynos850-pinctrl",
 		.data = &exynos850_of_data },
+	{ .compatible = "samsung,exynos8855-pinctrl",
+		.data = &exynos8855_of_data },
 	{ .compatible = "samsung,exynos8890-pinctrl",
 		.data = &exynos8890_of_data },
 	{ .compatible = "samsung,exynos8895-pinctrl",
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 937600430a6e..bb02fb49b2af 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -396,6 +396,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos7870_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
+extern const struct samsung_pinctrl_of_match_data exynos8855_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos8890_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos8895_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos9610_of_data;
-- 
2.34.1

Re: [PATCH v3 3/6] pinctrl: samsung: Add Exynos8855 pinctrl configuration

[Peter Griffin]

On Sat, 27 Jun 2026 at 17:54, Alim Akhtar <alim.akhtar@samsung.com> wrote:
>
> Add pinctrl configuration for Exynos8855. The bank type
> macros are reused from EXYNOS850 and GS101 SoC.
>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---

Reviewed-by: Peter Griffin <peter.griffin@linaro.org>

>  .../pinctrl/samsung/pinctrl-exynos-arm64.c    | 132 ++++++++++++++++++
>  drivers/pinctrl/samsung/pinctrl-samsung.c     |   2 +
>  drivers/pinctrl/samsung/pinctrl-samsung.h     |   1 +
>  3 files changed, 135 insertions(+)
>
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> index fe9f92cb037e..1aa977d2a1f8 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> @@ -943,6 +943,138 @@ const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = {
>         .num_ctrl       = ARRAY_SIZE(exynos850_pin_ctrl),
>  };
>
> +/* pin banks of exynos8855 pin-controller 0 (ALIVE) */
> +static const struct samsung_pin_bank_data exynos8855_pin_banks0[] __initconst = {
> +       GS101_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00, 0x00),
> +       GS101_PIN_BANK_EINTW(4, 0x020, "gpa1", 0x04, 0x08),
> +       EXYNOS850_PIN_BANK_EINTN(3, 0x040, "gpq0"),
> +       EXYNOS850_PIN_BANK_EINTN(2, 0x060, "gpq1"),
> +       GS101_PIN_BANK_EINTW(1, 0x080, "gpc0", 0x08, 0x10),
> +       GS101_PIN_BANK_EINTW(1, 0x0a0, "gpc1", 0x0c, 0x14),
> +       GS101_PIN_BANK_EINTW(1, 0x0c0, "gpc2", 0x10, 0x18),
> +       GS101_PIN_BANK_EINTW(1, 0x0e0, "gpc3", 0x14, 0x1c),
> +       GS101_PIN_BANK_EINTW(1, 0x100, "gpc4", 0x18, 0x20),
> +       GS101_PIN_BANK_EINTW(1, 0x120, "gpc5", 0x1c, 0x24),
> +       GS101_PIN_BANK_EINTW(1, 0x140, "gpc6", 0x20, 0x28),
> +       GS101_PIN_BANK_EINTW(1, 0x160, "gpc7", 0x24, 0x2c),
> +       GS101_PIN_BANK_EINTW(1, 0x180, "gpc8", 0x28, 0x30),
> +       GS101_PIN_BANK_EINTW(1, 0x1a0, "gpc9", 0x2c, 0x34),
> +       GS101_PIN_BANK_EINTW(1, 0x1c0, "gpc10", 0x30, 0x38),
> +       GS101_PIN_BANK_EINTW(1, 0x1e0, "gpc11", 0x34, 0x3c),
> +       GS101_PIN_BANK_EINTW(1, 0x200, "gpc12", 0x38, 0x40),
> +       GS101_PIN_BANK_EINTW(1, 0x220, "gpc13", 0x3c, 0x44),
> +       GS101_PIN_BANK_EINTW(1, 0x240, "gpc14", 0x40, 0x48),
> +       GS101_PIN_BANK_EINTW(1, 0x260, "gpj0", 0x44, 0x4c),
> +       GS101_PIN_BANK_EINTW(1, 0x280, "gpj1", 0x48, 0x50),
> +       GS101_PIN_BANK_EINTW(1, 0x2a0, "gpj2", 0x4c, 0x54),
> +};
> +
> +/* pin banks of exynos8855 pin-controller 1 (CMGP) */
> +static const struct samsung_pin_bank_data exynos8855_pin_banks1[] __initconst = {
> +       GS101_PIN_BANK_EINTW(1, 0x00,  "gpm0",  0x00, 0x00),
> +       GS101_PIN_BANK_EINTW(1, 0x20,  "gpm1",  0x04, 0x04),
> +       GS101_PIN_BANK_EINTW(1, 0x40,  "gpm2",  0x08, 0x08),
> +       GS101_PIN_BANK_EINTW(1, 0x60,  "gpm3",  0x0c, 0x0c),
> +       GS101_PIN_BANK_EINTW(1, 0x80,  "gpm4",  0x10, 0x10),
> +       GS101_PIN_BANK_EINTW(1, 0xa0,  "gpm5",  0x14, 0x14),
> +       GS101_PIN_BANK_EINTW(1, 0xc0,  "gpm6",  0x18, 0x18),
> +       GS101_PIN_BANK_EINTW(1, 0xe0,  "gpm7",  0x1c, 0x1c),
> +       GS101_PIN_BANK_EINTW(1, 0x100, "gpm8",  0x20, 0x20),
> +       GS101_PIN_BANK_EINTW(1, 0x120, "gpm9",  0x24, 0x24),
> +       GS101_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x28, 0x28),
> +       GS101_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x2c, 0x2c),
> +       GS101_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x30, 0x30),
> +       GS101_PIN_BANK_EINTW(1, 0x1a0, "gpm13", 0x34, 0x34),
> +       GS101_PIN_BANK_EINTW(1, 0x1c0, "gpm14", 0x38, 0x38),
> +       GS101_PIN_BANK_EINTW(1, 0x1e0, "gpm15", 0x3c, 0x3c),
> +       GS101_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40, 0x40),
> +       GS101_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44, 0x44),
> +       GS101_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x48, 0x48),
> +       GS101_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x4c, 0x4c),
> +       GS101_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x50, 0x50),
> +       GS101_PIN_BANK_EINTW(1, 0x2a0, "gpm21", 0x54, 0x54),
> +};
> +
> +/* pin banks of exynos8855 pin-controller 2 (HSI UFS) */
> +static const struct samsung_pin_bank_data exynos8855_pin_banks2[] __initconst = {
> +       GS101_PIN_BANK_EINTG(2, 0x0, "gpf3", 0x00, 0x00),
> +};
> +
> +/* pin banks of exynos8855 pin-controller 3 (PERIC) */
> +static const struct samsung_pin_bank_data exynos8855_pin_banks3[] __initconst = {
> +       GS101_PIN_BANK_EINTG(8, 0x0,   "gpp0", 0x00, 0x00),
> +       GS101_PIN_BANK_EINTG(8, 0x20,  "gpp1", 0x04, 0x08),
> +       GS101_PIN_BANK_EINTG(6, 0x40,  "gpp2", 0x08, 0x10),
> +       GS101_PIN_BANK_EINTG(4, 0x60,  "gpg0", 0x0c, 0x18),
> +       GS101_PIN_BANK_EINTG(3, 0x80,  "gpg1", 0x10, 0x1c),
> +       GS101_PIN_BANK_EINTG(6, 0xa0,  "gpb0", 0x14, 0x20),
> +       GS101_PIN_BANK_EINTG(4, 0xc0,  "gpb1", 0x18, 0x28),
> +};
> +
> +/* pin banks of exynos8855 pin-controller 4 (PERICMMC) */
> +static const struct samsung_pin_bank_data exynos8855_pin_banks4[] __initconst = {
> +       GS101_PIN_BANK_EINTG(7, 0x0, "gpf2", 0x00, 0x00),
> +};
> +
> +/* pin banks of exynos8855 pin-controller 5 (USI) */
> +static const struct samsung_pin_bank_data exynos8855_pin_banks5[] __initconst = {
> +       GS101_PIN_BANK_EINTG(8, 0x00, "gpp3", 0x00, 0x00),
> +       GS101_PIN_BANK_EINTG(2, 0x20, "gpp4", 0x04, 0x08),
> +       GS101_PIN_BANK_EINTG(2, 0x40, "gpg2", 0x08, 0x0c),
> +       GS101_PIN_BANK_EINTG(1, 0x60, "gpg3", 0x0c, 0x10),
> +};
> +
> +static const struct samsung_pin_ctrl exynos8855_pin_ctrl[] __initconst = {
> +       {
> +               /* pin-controller instance 0 ALIVE data */
> +               .pin_banks      = exynos8855_pin_banks0,
> +               .nr_banks       = ARRAY_SIZE(exynos8855_pin_banks0),
> +               .eint_wkup_init = exynos_eint_wkup_init,
> +               .suspend        = gs101_pinctrl_suspend,
> +               .resume         = gs101_pinctrl_resume,
> +       }, {
> +               /* pin-controller instance 1 CMGP data */
> +               .pin_banks      = exynos8855_pin_banks1,
> +               .nr_banks       = ARRAY_SIZE(exynos8855_pin_banks1),
> +               .eint_gpio_init = exynos_eint_gpio_init,
> +               .suspend        = gs101_pinctrl_suspend,
> +               .resume         = gs101_pinctrl_resume,
> +       }, {
> +               /* pin-controller instance 2 HSI UFS data */
> +               .pin_banks      = exynos8855_pin_banks2,
> +               .nr_banks       = ARRAY_SIZE(exynos8855_pin_banks2),
> +               .eint_gpio_init = exynos_eint_gpio_init,
> +               .suspend        = gs101_pinctrl_suspend,
> +               .resume         = gs101_pinctrl_resume,
> +       }, {
> +               /* pin-controller instance 3 PERIC data */
> +               .pin_banks      = exynos8855_pin_banks3,
> +               .nr_banks       = ARRAY_SIZE(exynos8855_pin_banks3),
> +               .eint_gpio_init = exynos_eint_gpio_init,
> +               .suspend        = gs101_pinctrl_suspend,
> +               .resume         = gs101_pinctrl_resume,
> +       }, {
> +               /* pin-controller instance 4 PERICMMC data */
> +               .pin_banks      = exynos8855_pin_banks4,
> +               .nr_banks       = ARRAY_SIZE(exynos8855_pin_banks4),
> +               .eint_gpio_init = exynos_eint_gpio_init,
> +               .suspend        = gs101_pinctrl_suspend,
> +               .resume         = gs101_pinctrl_resume,
> +       }, {
> +               /* pin-controller instance 5 USI data */
> +               .pin_banks      = exynos8855_pin_banks5,
> +               .nr_banks       = ARRAY_SIZE(exynos8855_pin_banks5),
> +               .eint_gpio_init = exynos_eint_gpio_init,
> +               .suspend        = gs101_pinctrl_suspend,
> +               .resume         = gs101_pinctrl_resume,
> +       },
> +};
> +
> +const struct samsung_pinctrl_of_match_data exynos8855_of_data __initconst = {
> +       .ctrl           = exynos8855_pin_ctrl,
> +       .num_ctrl       = ARRAY_SIZE(exynos8855_pin_ctrl),
> +};
> +
>  /* pin banks of exynos990 pin-controller 0 (ALIVE) */
>  static struct samsung_pin_bank_data exynos990_pin_banks0[] = {
>         /* Must start with EINTG banks, ordered by EINT group number. */
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
> index 5ac6f6b02327..5ecc9ed4c44d 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.c
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
> @@ -1500,6 +1500,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
>                 .data = &exynos7885_of_data },
>         { .compatible = "samsung,exynos850-pinctrl",
>                 .data = &exynos850_of_data },
> +       { .compatible = "samsung,exynos8855-pinctrl",
> +               .data = &exynos8855_of_data },
>         { .compatible = "samsung,exynos8890-pinctrl",
>                 .data = &exynos8890_of_data },
>         { .compatible = "samsung,exynos8895-pinctrl",
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
> index 937600430a6e..bb02fb49b2af 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.h
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
> @@ -396,6 +396,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
>  extern const struct samsung_pinctrl_of_match_data exynos7870_of_data;
>  extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
>  extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
> +extern const struct samsung_pinctrl_of_match_data exynos8855_of_data;
>  extern const struct samsung_pinctrl_of_match_data exynos8890_of_data;
>  extern const struct samsung_pinctrl_of_match_data exynos8895_of_data;
>  extern const struct samsung_pinctrl_of_match_data exynos9610_of_data;
> --
> 2.34.1
>

[PATCH v3 4/6] dt-bindings: pinctrl: samsung: Add exynos8855-wakeup-eint compatible

[Alim Akhtar]

Add a dedicated compatible for the exynos8855-wakeup-eint node, which
is compatible with Exynos7 implementation.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 .../bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
index 2b88f25e80a6..802911e23aff 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
@@ -41,6 +41,7 @@ properties:
               - samsung,exynos7870-wakeup-eint
               - samsung,exynos7885-wakeup-eint
               - samsung,exynos850-wakeup-eint
+              - samsung,exynos8855-wakeup-eint
               - samsung,exynos8890-wakeup-eint
               - samsung,exynos8895-wakeup-eint
           - const: samsung,exynos7-wakeup-eint
-- 
2.34.1

Re: [PATCH v3 4/6] dt-bindings: pinctrl: samsung: Add exynos8855-wakeup-eint compatible

[Peter Griffin]

On Sat, 27 Jun 2026 at 17:54, Alim Akhtar <alim.akhtar@samsung.com> wrote:
>
> Add a dedicated compatible for the exynos8855-wakeup-eint node, which
> is compatible with Exynos7 implementation.
>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---

Reviewed-by: Peter Griffin <peter.griffin@linaro.org>

>  .../bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml       | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
> index 2b88f25e80a6..802911e23aff 100644
> --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
> @@ -41,6 +41,7 @@ properties:
>                - samsung,exynos7870-wakeup-eint
>                - samsung,exynos7885-wakeup-eint
>                - samsung,exynos850-wakeup-eint
> +              - samsung,exynos8855-wakeup-eint
>                - samsung,exynos8890-wakeup-eint
>                - samsung,exynos8895-wakeup-eint
>            - const: samsung,exynos7-wakeup-eint
> --
> 2.34.1
>

[PATCH v3 5/6] arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk

[Alim Akhtar]

Add initial devicetree support for Samsung smdk board using
Exynos8855 SoC.
This SoC has Octa-core CPU with tri cluster architecture, a custom GPU
and a NPU supporting up to 14.7 TOPS apart from other supporting peripheral
and IPs.

Commercially this SoC is also known as Exynos1580 [1]

[1] https://semiconductor.samsung.com/processor/mobile-processor/exynos-1580/

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 arch/arm64/boot/dts/exynos/Makefile           |   1 +
 .../boot/dts/exynos/exynos8855-pinctrl.dtsi   | 574 ++++++++++++++++++
 .../arm64/boot/dts/exynos/exynos8855-smdk.dts |  32 +
 arch/arm64/boot/dts/exynos/exynos8855.dtsi    | 204 +++++++
 4 files changed, 811 insertions(+)
 create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
 create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
 create mode 100644 arch/arm64/boot/dts/exynos/exynos8855.dtsi

diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
index 76cc23acb9b2..8c48ce2e02e5 100644
--- a/arch/arm64/boot/dts/exynos/Makefile
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \
 	exynos7870-on7xelte.dtb		\
 	exynos7885-jackpotlte.dtb	\
 	exynos850-e850-96.dtb		\
+	exynos8855-smdk.dtb		\
 	exynos8895-dreamlte.dtb		\
 	exynos9810-starlte.dtb		\
 	exynos990-c1s.dtb		\
diff --git a/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
new file mode 100644
index 000000000000..b65f1698cd74
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
@@ -0,0 +1,574 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's S5E8855 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2023 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Samsung's S5E8855 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "exynos-pinctrl.h"
+
+&pinctrl_alive {
+	gpa0: gpa0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpa1: gpa1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpq0: gpq0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpq1: gpq1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpc0: gpc0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpc1: gpc1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpc2: gpc2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpc3: gpc3-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpc4: gpc4-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpc5: gpc5-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpc6: gpc6-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpc7: gpc7-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpc8: gpc8-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpc9: gpc9-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpc10: gpc10-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpc11: gpc11-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpc12: gpc12-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpc13: gpc13-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpc14: gpc14-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpj0: gpj0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpj1: gpj1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpj2: gpj2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};
+
+&pinctrl_cmgp {
+	gpm0: gpm0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm1: gpm1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm2: gpm2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm3: gpm3-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm4: gpm4-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm5: gpm5-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm6: gpm6-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm7: gpm7-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm8: gpm8-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm9: gpm9-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm10: gpm10-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm11: gpm11-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm12: gpm12-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm13: gpm13-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm14: gpm14-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm15: gpm15-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm16: gpm16-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm17: gpm17-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm18: gpm18-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm19: gpm19-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm20: gpm20-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm21: gpm21-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};
+
+&pinctrl_hsi_ufs {
+	gpf3: gpf3-gpio-bank{
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_peric {
+	gpp0: gpp0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp1: gpp1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp2: gpp2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpg0: gpg0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpg1: gpg1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpb0: gpb0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpb1: gpb1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_pericmmc {
+	gpf2: gpf2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_usi {
+	gpp3: gpp3-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp4: gpp4-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpg2: gpg2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpg3: gpg3-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos8855-smdk.dts b/arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
new file mode 100644
index 000000000000..792d52affc61
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung Exynos8855 SMDK board device tree source
+ *
+ * Copyright (C) 2023 Samsung Electronics Co., Ltd.
+ *
+ * Device tree source file for Samsung SMDK board which is based on
+ * Exynos8855 SoC.
+ */
+
+/dts-v1/;
+
+#include "exynos8855.dtsi"
+
+/ {
+	model = "Samsung Exynos8855 SMDK board";
+	compatible = "samsung,exynos8855-smdk","samsung,exynos8855";
+
+	chosen {
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x80000000>;
+	};
+
+};
+
+&oscclk {
+	clock-frequency = <76800000>;
+};
+
diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
new file mode 100644
index 000000000000..9d82fceb5130
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung Exynos8855 SoC device tree source
+ *
+ * Copyright (C) 2023 Samsung Electronics Co., Ltd.
+ *
+ * Samsung Exynos8855 SoC device nodes are listed in this file.
+ * Exynos8855 based board files can include this file and provide
+ * values for board specific bindings.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "samsung,exynos8855";
+	#address-cells = <2>;
+	#size-cells = <1>;
+
+	interrupt-parent = <&gic>;
+
+	aliases {
+		pinctrl0 = &pinctrl_alive;
+		pinctrl1 = &pinctrl_cmgp;
+		pinctrl2 = &pinctrl_hsi_ufs;
+		pinctrl3 = &pinctrl_peric;
+		pinctrl4 = &pinctrl_pericmmc;
+		pinctrl5 = &pinctrl_usi;
+	};
+
+	oscclk: clock-oscclk {
+		compatible = "fixed-clock";
+		clock-output-names = "oscclk";
+		#clock-cells = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+				core2 {
+					cpu = <&cpu2>;
+				};
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+				core1 {
+					cpu = <&cpu5>;
+				};
+				core2 {
+					cpu = <&cpu6>;
+				};
+			};
+
+			cluster2 {
+				core0 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a520";
+			reg = <0x0>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a520";
+			reg = <0x100>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a520";
+			reg = <0x200>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a520";
+			reg = <0x300>;
+			enable-method = "psci";
+		};
+
+		cpu4: cpu@400 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a720";
+			reg = <0x400>;
+			enable-method = "psci";
+		};
+
+		cpu5: cpu@500 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a720";
+			reg = <0x500>;
+			enable-method = "psci";
+		};
+
+		cpu6: cpu@600 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a720";
+			reg = <0x600>;
+			enable-method = "psci";
+		};
+
+		cpu7: cpu@700 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a720";
+			reg = <0x700>;
+			enable-method = "psci";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x0 0x20000000>;
+
+		gic: interrupt-controller@10200000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x10200000 0x10000>,
+			      <0x10240000 0x140000>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_alive: pinctrl@11850000 {
+			compatible = "samsung,exynos8855-pinctrl";
+			reg = <0x11850000 0x1000>;
+
+			wakeup-interrupt-controller {
+				compatible = "samsung,exynos8855-wakeup-eint",
+					     "samsung,exynos7-wakeup-eint";
+			};
+		};
+
+		pinctrl_cmgp: pinctrl@12030000 {
+			compatible = "samsung,exynos8855-pinctrl";
+			reg = <0x12030000 0x1000>;
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_usi: pinctrl@15030000 {
+			compatible = "samsung,exynos8855-pinctrl";
+			reg = <0x15030000 0x1000>;
+			interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_peric: pinctrl@15440000 {
+			compatible = "samsung,exynos8855-pinctrl";
+			reg = <0x15440000 0x1000>;
+			interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_pericmmc: pinctrl@154f0000 {
+			compatible = "samsung,exynos8855-pinctrl";
+			reg = <0x154f0000 0x1000>;
+			interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_hsi_ufs: pinctrl@17040000 {
+			compatible = "samsung,exynos8855-pinctrl";
+			reg = <0x17040000 0x1000>;
+			interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		/* Hypervisor Virtual Timer interrupt is not wired to GIC */
+		interrupts =
+		     <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+		     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+		     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+		     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+#include "exynos8855-pinctrl.dtsi"
-- 
2.34.1

Re: [PATCH v3 5/6] arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk

[Peter Griffin]

On Sat, 27 Jun 2026 at 17:54, Alim Akhtar <alim.akhtar@samsung.com> wrote:
>
> Add initial devicetree support for Samsung smdk board using
> Exynos8855 SoC.
> This SoC has Octa-core CPU with tri cluster architecture, a custom GPU
> and a NPU supporting up to 14.7 TOPS apart from other supporting peripheral
> and IPs.
>
> Commercially this SoC is also known as Exynos1580 [1]
>
> [1] https://semiconductor.samsung.com/processor/mobile-processor/exynos-1580/
>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/Makefile           |   1 +
>  .../boot/dts/exynos/exynos8855-pinctrl.dtsi   | 574 ++++++++++++++++++
>  .../arm64/boot/dts/exynos/exynos8855-smdk.dts |  32 +
>  arch/arm64/boot/dts/exynos/exynos8855.dtsi    | 204 +++++++
>  4 files changed, 811 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
>  create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
>  create mode 100644 arch/arm64/boot/dts/exynos/exynos8855.dtsi
>
> diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
> index 76cc23acb9b2..8c48ce2e02e5 100644
> --- a/arch/arm64/boot/dts/exynos/Makefile
> +++ b/arch/arm64/boot/dts/exynos/Makefile
> @@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \
>         exynos7870-on7xelte.dtb         \
>         exynos7885-jackpotlte.dtb       \
>         exynos850-e850-96.dtb           \
> +       exynos8855-smdk.dtb             \
>         exynos8895-dreamlte.dtb         \
>         exynos9810-starlte.dtb          \
>         exynos990-c1s.dtb               \
> diff --git a/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
> new file mode 100644
> index 000000000000..b65f1698cd74
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
> @@ -0,0 +1,574 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Samsung's S5E8855 SoC pin-mux and pin-config device tree source
> + *
> + * Copyright (c) 2023 Samsung Electronics Co., Ltd.
> + *             http://www.samsung.com
> + *
> + * Samsung's S5E8855 SoC pin-mux and pin-config options are listed as device
> + * tree nodes are listed in this file.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include "exynos-pinctrl.h"
> +
> +&pinctrl_alive {
> +       gpa0: gpa0-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> +                            <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> +                            <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> +                            <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +                            <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +                            <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> +                            <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> +                            <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpa1: gpa1-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +                            <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> +                            <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> +                            <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +                            <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpq0: gpq0-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +       };
> +
> +       gpq1: gpq1-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +       };
> +
> +       gpc0: gpc0-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpc1: gpc1-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpc2: gpc2-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpc3: gpc3-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpc4: gpc4-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpc5: gpc5-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpc6: gpc6-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpc7: gpc7-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpc8: gpc8-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpc9: gpc9-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpc10: gpc10-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpc11: gpc11-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpc12: gpc12-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpc13: gpc13-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpc14: gpc14-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpj0: gpj0-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpj1: gpj1-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpj2: gpj2-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +};
> +
> +&pinctrl_cmgp {
> +       gpm0: gpm0-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm1: gpm1-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm2: gpm2-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm3: gpm3-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm4: gpm4-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm5: gpm5-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm6: gpm6-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm7: gpm7-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm8: gpm8-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm9: gpm9-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm10: gpm10-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm11: gpm11-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm12: gpm12-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm13: gpm13-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm14: gpm14-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm15: gpm15-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm16: gpm16-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm17: gpm17-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm18: gpm18-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm19: gpm19-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm20: gpm20-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpm21: gpm21-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +};
> +
> +&pinctrl_hsi_ufs {
> +       gpf3: gpf3-gpio-bank{
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +};
> +
> +&pinctrl_peric {
> +       gpp0: gpp0-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp1: gpp1-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp2: gpp2-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpg0: gpg0-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpg1: gpg1-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpb0: gpb0-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpb1: gpb1-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +};
> +
> +&pinctrl_pericmmc {
> +       gpf2: gpf2-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +};
> +
> +&pinctrl_usi {
> +       gpp3: gpp3-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp4: gpp4-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpg2: gpg2-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpg3: gpg3-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +};
> diff --git a/arch/arm64/boot/dts/exynos/exynos8855-smdk.dts b/arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
> new file mode 100644
> index 000000000000..792d52affc61
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
> @@ -0,0 +1,32 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Samsung Exynos8855 SMDK board device tree source
> + *
> + * Copyright (C) 2023 Samsung Electronics Co., Ltd.
> + *
> + * Device tree source file for Samsung SMDK board which is based on
> + * Exynos8855 SoC.
> + */
> +
> +/dts-v1/;
> +
> +#include "exynos8855.dtsi"
> +
> +/ {
> +       model = "Samsung Exynos8855 SMDK board";
> +       compatible = "samsung,exynos8855-smdk","samsung,exynos8855";
> +
> +       chosen {
> +       };
> +
> +       memory@80000000 {
> +               device_type = "memory";
> +               reg = <0x0 0x80000000 0x80000000>;
> +       };
> +
> +};
> +
> +&oscclk {
> +       clock-frequency = <76800000>;
> +};
> +
> diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
> new file mode 100644
> index 000000000000..9d82fceb5130
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
> @@ -0,0 +1,204 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Samsung Exynos8855 SoC device tree source
> + *
> + * Copyright (C) 2023 Samsung Electronics Co., Ltd.
> + *
> + * Samsung Exynos8855 SoC device nodes are listed in this file.
> + * Exynos8855 based board files can include this file and provide
> + * values for board specific bindings.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +       compatible = "samsung,exynos8855";
> +       #address-cells = <2>;
> +       #size-cells = <1>;
> +
> +       interrupt-parent = <&gic>;
> +
> +       aliases {
> +               pinctrl0 = &pinctrl_alive;
> +               pinctrl1 = &pinctrl_cmgp;
> +               pinctrl2 = &pinctrl_hsi_ufs;
> +               pinctrl3 = &pinctrl_peric;
> +               pinctrl4 = &pinctrl_pericmmc;
> +               pinctrl5 = &pinctrl_usi;
> +       };
> +
> +       oscclk: clock-oscclk {
> +               compatible = "fixed-clock";
> +               clock-output-names = "oscclk";
> +               #clock-cells = <0>;
> +       };

Small nit, but I believe oscclk node should be ordered
alpha-numerically by the node name. See
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html

Peter

> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               cpu-map {
> +                       cluster0 {
> +                               core0 {
> +                                       cpu = <&cpu0>;
> +                               };
> +                               core1 {
> +                                       cpu = <&cpu1>;
> +                               };
> +                               core2 {
> +                                       cpu = <&cpu2>;
> +                               };
> +                               core3 {
> +                                       cpu = <&cpu3>;
> +                               };
> +                       };
> +
> +                       cluster1 {
> +                               core0 {
> +                                       cpu = <&cpu4>;
> +                               };
> +                               core1 {
> +                                       cpu = <&cpu5>;
> +                               };
> +                               core2 {
> +                                       cpu = <&cpu6>;
> +                               };
> +                       };
> +
> +                       cluster2 {
> +                               core0 {
> +                                       cpu = <&cpu7>;
> +                               };
> +                       };
> +               };
> +
> +               cpu0: cpu@0 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a520";
> +                       reg = <0x0>;
> +                       enable-method = "psci";
> +               };
> +
> +               cpu1: cpu@100 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a520";
> +                       reg = <0x100>;
> +                       enable-method = "psci";
> +               };
> +
> +               cpu2: cpu@200 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a520";
> +                       reg = <0x200>;
> +                       enable-method = "psci";
> +               };
> +
> +               cpu3: cpu@300 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a520";
> +                       reg = <0x300>;
> +                       enable-method = "psci";
> +               };
> +
> +               cpu4: cpu@400 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a720";
> +                       reg = <0x400>;
> +                       enable-method = "psci";
> +               };
> +
> +               cpu5: cpu@500 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a720";
> +                       reg = <0x500>;
> +                       enable-method = "psci";
> +               };
> +
> +               cpu6: cpu@600 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a720";
> +                       reg = <0x600>;
> +                       enable-method = "psci";
> +               };
> +
> +               cpu7: cpu@700 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a720";
> +                       reg = <0x700>;
> +                       enable-method = "psci";
> +               };
> +       };
> +
> +       psci {
> +               compatible = "arm,psci-1.0";
> +               method = "smc";
> +       };
> +
> +       soc: soc@0 {
> +               compatible = "simple-bus";
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               ranges = <0x0 0x0 0x0 0x20000000>;
> +
> +               gic: interrupt-controller@10200000 {
> +                       compatible = "arm,gic-v3";
> +                       #interrupt-cells = <3>;
> +                       interrupt-controller;
> +                       reg = <0x10200000 0x10000>,
> +                             <0x10240000 0x140000>;
> +                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +               };
> +
> +               pinctrl_alive: pinctrl@11850000 {
> +                       compatible = "samsung,exynos8855-pinctrl";
> +                       reg = <0x11850000 0x1000>;
> +
> +                       wakeup-interrupt-controller {
> +                               compatible = "samsung,exynos8855-wakeup-eint",
> +                                            "samsung,exynos7-wakeup-eint";
> +                       };
> +               };
> +
> +               pinctrl_cmgp: pinctrl@12030000 {
> +                       compatible = "samsung,exynos8855-pinctrl";
> +                       reg = <0x12030000 0x1000>;
> +                       interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> +               };
> +
> +               pinctrl_usi: pinctrl@15030000 {
> +                       compatible = "samsung,exynos8855-pinctrl";
> +                       reg = <0x15030000 0x1000>;
> +                       interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
> +               };
> +
> +               pinctrl_peric: pinctrl@15440000 {
> +                       compatible = "samsung,exynos8855-pinctrl";
> +                       reg = <0x15440000 0x1000>;
> +                       interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
> +               };
> +
> +               pinctrl_pericmmc: pinctrl@154f0000 {
> +                       compatible = "samsung,exynos8855-pinctrl";
> +                       reg = <0x154f0000 0x1000>;
> +                       interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
> +               };
> +
> +               pinctrl_hsi_ufs: pinctrl@17040000 {
> +                       compatible = "samsung,exynos8855-pinctrl";
> +                       reg = <0x17040000 0x1000>;
> +                       interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
> +               };
> +       };
> +
> +       timer {
> +               compatible = "arm,armv8-timer";
> +               /* Hypervisor Virtual Timer interrupt is not wired to GIC */
> +               interrupts =
> +                    <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> +                    <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> +                    <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> +                    <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> +       };
> +};
> +
> +#include "exynos8855-pinctrl.dtsi"
> --
> 2.34.1
>

RE: [PATCH v3 5/6] arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk

[Alim Akhtar]

> -----Original Message-----
> From: Peter Griffin <peter.griffin@linaro.org>
> Sent: Thursday, July 9, 2026 7:20 PM
> To: Alim Akhtar <alim.akhtar@samsung.com>
> Cc: krzk@kernel.org; robh@kernel.org; conor+dt@kernel.org;
> linusw@kernel.org; linux-samsung-soc@vger.kernel.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-
> gpio@vger.kernel.org; hajun.sung@samsung.com
> Subject: Re: [PATCH v3 5/6] arm64: dts: exynos: add initial support for Samsung
> Exynos8855 smdk
> 
> On Sat, 27 Jun 2026 at 17:54, Alim Akhtar <alim.akhtar@samsung.com> wrote:
> >
> > Add initial devicetree support for Samsung smdk board using
> > Exynos8855 SoC.
> > This SoC has Octa-core CPU with tri cluster architecture, a custom GPU
> > and a NPU supporting up to 14.7 TOPS apart from other supporting
> > peripheral and IPs.
> >
> > Commercially this SoC is also known as Exynos1580 [1]
> >
> > [1]
> > https://semiconductor.samsung.com/processor/mobile-processor/exynos-15
> > 80/
> >
> > Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> > ---
> >  arch/arm64/boot/dts/exynos/Makefile           |   1 +
> >  .../boot/dts/exynos/exynos8855-pinctrl.dtsi   | 574 ++++++++++++++++++
> >  .../arm64/boot/dts/exynos/exynos8855-smdk.dts |  32 +
> >  arch/arm64/boot/dts/exynos/exynos8855.dtsi    | 204 +++++++
> >  4 files changed, 811 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
> >  create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
> >  create mode 100644 arch/arm64/boot/dts/exynos/exynos8855.dtsi
> > +       };
[snip]
> > +
> > +       oscclk: clock-oscclk {
> > +               compatible = "fixed-clock";
> > +               clock-output-names = "oscclk";
> > +               #clock-cells = <0>;
> > +       };
> 
> Small nit, but I believe oscclk node should be ordered alpha-numerically by the
> node name. See https://docs.kernel.org/devicetree/bindings/dts-coding-
> style.html
> 
Thanks, will update in v4 

> Peter
> 

Re: [PATCH v3 5/6] arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk

[Krzysztof Kozlowski]

On 10/07/2026 11:55, Alim Akhtar wrote:
>>> ---
>>>  arch/arm64/boot/dts/exynos/Makefile           |   1 +
>>>  .../boot/dts/exynos/exynos8855-pinctrl.dtsi   | 574 ++++++++++++++++++
>>>  .../arm64/boot/dts/exynos/exynos8855-smdk.dts |  32 +
>>>  arch/arm64/boot/dts/exynos/exynos8855.dtsi    | 204 +++++++
>>>  4 files changed, 811 insertions(+)
>>>  create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
>>>  create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
>>>  create mode 100644 arch/arm64/boot/dts/exynos/exynos8855.dtsi
>>> +       };
> [snip]
>>> +
>>> +       oscclk: clock-oscclk {
>>> +               compatible = "fixed-clock";
>>> +               clock-output-names = "oscclk";
>>> +               #clock-cells = <0>;
>>> +       };
>>
>> Small nit, but I believe oscclk node should be ordered alpha-numerically by the
>> node name. See https://docs.kernel.org/devicetree/bindings/dts-coding-
>> style.html
>>
> Thanks, will update in v4 


The node feels ordered, no? clock before cpu?

Best regards,
Krzysztof

Re: [PATCH v3 5/6] arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk

[Peter Griffin]

Hi Krysztof,

On Fri, 10 Jul 2026 at 11:00, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 10/07/2026 11:55, Alim Akhtar wrote:
> >>> ---
> >>>  arch/arm64/boot/dts/exynos/Makefile           |   1 +
> >>>  .../boot/dts/exynos/exynos8855-pinctrl.dtsi   | 574 ++++++++++++++++++
> >>>  .../arm64/boot/dts/exynos/exynos8855-smdk.dts |  32 +
> >>>  arch/arm64/boot/dts/exynos/exynos8855.dtsi    | 204 +++++++
> >>>  4 files changed, 811 insertions(+)
> >>>  create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
> >>>  create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
> >>>  create mode 100644 arch/arm64/boot/dts/exynos/exynos8855.dtsi
> >>> +       };
> > [snip]
> >>> +
> >>> +       oscclk: clock-oscclk {
> >>> +               compatible = "fixed-clock";
> >>> +               clock-output-names = "oscclk";
> >>> +               #clock-cells = <0>;
> >>> +       };
> >>
> >> Small nit, but I believe oscclk node should be ordered alpha-numerically by the
> >> node name. See https://docs.kernel.org/devicetree/bindings/dts-coding-
> >> style.html
> >>
> > Thanks, will update in v4
>
>
> The node feels ordered, no? clock before cpu?

Yes, good point. I was looking at the label not the node name.

Peter

RE: [PATCH v3 5/6] arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk

[Alim Akhtar]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: Friday, July 10, 2026 3:30 PM
> To: Alim Akhtar <alim.akhtar@samsung.com>; 'Peter Griffin'
> <peter.griffin@linaro.org>
> Cc: robh@kernel.org; conor+dt@kernel.org; linusw@kernel.org; linux-samsung-
> soc@vger.kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; linux-gpio@vger.kernel.org;
> hajun.sung@samsung.com
> Subject: Re: [PATCH v3 5/6] arm64: dts: exynos: add initial support for Samsung
> Exynos8855 smdk
> 
> On 10/07/2026 11:55, Alim Akhtar wrote:
> >>> ---
> >>>  arch/arm64/boot/dts/exynos/Makefile           |   1 +
> >>>  .../boot/dts/exynos/exynos8855-pinctrl.dtsi   | 574 ++++++++++++++++++
> >>>  .../arm64/boot/dts/exynos/exynos8855-smdk.dts |  32 +
> >>>  arch/arm64/boot/dts/exynos/exynos8855.dtsi    | 204 +++++++
> >>>  4 files changed, 811 insertions(+)
> >>>  create mode 100644
> >>> arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
> >>>  create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
> >>>  create mode 100644 arch/arm64/boot/dts/exynos/exynos8855.dtsi
> >>> +       };
> > [snip]
> >>> +
> >>> +       oscclk: clock-oscclk {
> >>> +               compatible = "fixed-clock";
> >>> +               clock-output-names = "oscclk";
> >>> +               #clock-cells = <0>;
> >>> +       };
> >>
> >> Small nit, but I believe oscclk node should be ordered
> >> alpha-numerically by the node name. See
> >> https://docs.kernel.org/devicetree/bindings/dts-coding-
> >> style.html
> >>
> > Thanks, will update in v4
> 
> 
> The node feels ordered, no? clock before cpu?
> 
Right, " ordered alpha-numerically by the node name"

Krzysztof, do you want to send v4 with all the reviewed-by tag collected? 


> Best regards,
> Krzysztof

Re: [PATCH v3 5/6] arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk

[Krzysztof Kozlowski]

On 10/07/2026 12:20, Alim Akhtar wrote:
> 
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@kernel.org>
>> Sent: Friday, July 10, 2026 3:30 PM
>> To: Alim Akhtar <alim.akhtar@samsung.com>; 'Peter Griffin'
>> <peter.griffin@linaro.org>
>> Cc: robh@kernel.org; conor+dt@kernel.org; linusw@kernel.org; linux-samsung-
>> soc@vger.kernel.org; linux-kernel@vger.kernel.org;
>> devicetree@vger.kernel.org; linux-gpio@vger.kernel.org;
>> hajun.sung@samsung.com
>> Subject: Re: [PATCH v3 5/6] arm64: dts: exynos: add initial support for Samsung
>> Exynos8855 smdk
>>
>> On 10/07/2026 11:55, Alim Akhtar wrote:
>>>>> ---
>>>>>  arch/arm64/boot/dts/exynos/Makefile           |   1 +
>>>>>  .../boot/dts/exynos/exynos8855-pinctrl.dtsi   | 574 ++++++++++++++++++
>>>>>  .../arm64/boot/dts/exynos/exynos8855-smdk.dts |  32 +
>>>>>  arch/arm64/boot/dts/exynos/exynos8855.dtsi    | 204 +++++++
>>>>>  4 files changed, 811 insertions(+)
>>>>>  create mode 100644
>>>>> arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
>>>>>  create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
>>>>>  create mode 100644 arch/arm64/boot/dts/exynos/exynos8855.dtsi
>>>>> +       };
>>> [snip]
>>>>> +
>>>>> +       oscclk: clock-oscclk {
>>>>> +               compatible = "fixed-clock";
>>>>> +               clock-output-names = "oscclk";
>>>>> +               #clock-cells = <0>;
>>>>> +       };
>>>>
>>>> Small nit, but I believe oscclk node should be ordered
>>>> alpha-numerically by the node name. See
>>>> https://docs.kernel.org/devicetree/bindings/dts-coding-
>>>> style.html
>>>>
>>> Thanks, will update in v4
>>
>>
>> The node feels ordered, no? clock before cpu?
>>
> Right, " ordered alpha-numerically by the node name"
> 
> Krzysztof, do you want to send v4 with all the reviewed-by tag collected? 

No need, there are no changes planned, right? I just give it a day or
two if Peter or someone wants to review this one in such case.

Best regards,
Krzysztof

RE: [PATCH v3 5/6] arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk

[Alim Akhtar]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: Friday, July 10, 2026 3:55 PM
> To: Alim Akhtar <alim.akhtar@samsung.com>; 'Peter Griffin'
> <peter.griffin@linaro.org>
> Cc: robh@kernel.org; conor+dt@kernel.org; linusw@kernel.org; linux-samsung-
> soc@vger.kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; linux-gpio@vger.kernel.org;
> hajun.sung@samsung.com
> Subject: Re: [PATCH v3 5/6] arm64: dts: exynos: add initial support for Samsung
> Exynos8855 smdk
> 
> On 10/07/2026 12:20, Alim Akhtar wrote:
> >
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <krzk@kernel.org>
> >> Sent: Friday, July 10, 2026 3:30 PM
> >> To: Alim Akhtar <alim.akhtar@samsung.com>; 'Peter Griffin'
> >> <peter.griffin@linaro.org>
> >> Cc: robh@kernel.org; conor+dt@kernel.org; linusw@kernel.org;
> >> linux-samsung- soc@vger.kernel.org; linux-kernel@vger.kernel.org;
> >> devicetree@vger.kernel.org; linux-gpio@vger.kernel.org;
> >> hajun.sung@samsung.com
> >> Subject: Re: [PATCH v3 5/6] arm64: dts: exynos: add initial support
> >> for Samsung
> >> Exynos8855 smdk
> >>
> >> On 10/07/2026 11:55, Alim Akhtar wrote:
> >>>>> ---
> >>>>>  arch/arm64/boot/dts/exynos/Makefile           |   1 +
> >>>>>  .../boot/dts/exynos/exynos8855-pinctrl.dtsi   | 574
> ++++++++++++++++++
> >>>>>  .../arm64/boot/dts/exynos/exynos8855-smdk.dts |  32 +
> >>>>>  arch/arm64/boot/dts/exynos/exynos8855.dtsi    | 204 +++++++
> >>>>>  4 files changed, 811 insertions(+)  create mode 100644
> >>>>> arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
> >>>>>  create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
> >>>>>  create mode 100644 arch/arm64/boot/dts/exynos/exynos8855.dtsi
> >>>>> +       };
> >>> [snip]
> >>>>> +
> >>>>> +       oscclk: clock-oscclk {
> >>>>> +               compatible = "fixed-clock";
> >>>>> +               clock-output-names = "oscclk";
> >>>>> +               #clock-cells = <0>;
> >>>>> +       };
> >>>>
> >>>> Small nit, but I believe oscclk node should be ordered
> >>>> alpha-numerically by the node name. See
> >>>> https://docs.kernel.org/devicetree/bindings/dts-coding-
> >>>> style.html
> >>>>
> >>> Thanks, will update in v4
> >>
> >>
> >> The node feels ordered, no? clock before cpu?
> >>
> > Right, " ordered alpha-numerically by the node name"
> >
> > Krzysztof, do you want to send v4 with all the reviewed-by tag collected?
> 
> No need, there are no changes planned, right? I just give it a day or two if Peter
> or someone wants to review this one in such case.
> 
Sure, no changes for now. 
Thanks!

> Best regards,
> Krzysztof

[PATCH v3 6/6] MAINTAINERS: Add entry for Samsung Exynos8855 SoC

[Alim Akhtar]

Add maintainers entry for the Samsung Exynos8855 SoC based platforms

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 MAINTAINERS | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 1705eb823dd0..f6d9e03d3370 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -23996,6 +23996,13 @@ F:	arch/arm64/boot/dts/exynos/exynos850*
 F:	drivers/clk/samsung/clk-exynos850.c
 F:	include/dt-bindings/clock/exynos850.h
 
+SAMSUNG EXYNOS8855 SoC SUPPORT
+M:	Alim Akhtar <alim.akhtar@samsung.com>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L:	linux-samsung-soc@vger.kernel.org
+S:	Maintained
+F:	arch/arm64/boot/dts/exynos/exynos8855*
+
 SAMSUNG EXYNOS ACPM MAILBOX PROTOCOL
 M:	Tudor Ambarus <tudor.ambarus@linaro.org>
 L:	linux-kernel@vger.kernel.org
-- 
2.34.1

Re: [PATCH v3 6/6] MAINTAINERS: Add entry for Samsung Exynos8855 SoC

[Peter Griffin]

On Sat, 27 Jun 2026 at 17:54, Alim Akhtar <alim.akhtar@samsung.com> wrote:
>
> Add maintainers entry for the Samsung Exynos8855 SoC based platforms
>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---

Reviewed-by: Peter Griffin <peter.griffin@linaro.org>

>  MAINTAINERS | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1705eb823dd0..f6d9e03d3370 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -23996,6 +23996,13 @@ F:     arch/arm64/boot/dts/exynos/exynos850*
>  F:     drivers/clk/samsung/clk-exynos850.c
>  F:     include/dt-bindings/clock/exynos850.h
>
> +SAMSUNG EXYNOS8855 SoC SUPPORT
> +M:     Alim Akhtar <alim.akhtar@samsung.com>
> +L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> +L:     linux-samsung-soc@vger.kernel.org
> +S:     Maintained
> +F:     arch/arm64/boot/dts/exynos/exynos8855*
> +
>  SAMSUNG EXYNOS ACPM MAILBOX PROTOCOL
>  M:     Tudor Ambarus <tudor.ambarus@linaro.org>
>  L:     linux-kernel@vger.kernel.org
> --
> 2.34.1
>

Re: (subset) [PATCH v3 0/6] Add minimal Exynos8855 SoC support

[Krzysztof Kozlowski]

On Sat, 27 Jun 2026 22:42:22 +0530, Alim Akhtar wrote:
> This series adds initial support for the Exynos8855 SoC and also
> initial SMDK board support.
> 
> Exynos8855 is octa-core CPUs, a combination of Cortex-A720 and Cortex-A520,
> arranged in 3 clusters. And other peripheral for mobile application.
> 
> This initial support consists of CPUs, pinctrl and related nodes
> needed for initial kernel boot.
> 
> [...]

Applied, thanks!

[2/6] dt-binding: pinctrl: samsung: Add exynos8855-pinctrl compatible
      https://git.kernel.org/pinctrl/samsung/c/8e8bad1e2ab599174c21dd2d0ba6fcf5f82dafa5
[3/6] pinctrl: samsung: Add Exynos8855 pinctrl configuration
      https://git.kernel.org/pinctrl/samsung/c/d441836c9d704d0f3db5dbf44df87af2ba7a9d26
[4/6] dt-bindings: pinctrl: samsung: Add exynos8855-wakeup-eint compatible
      https://git.kernel.org/pinctrl/samsung/c/7cd3475913736239696e0111d4d5845d9e0a79b6

Best regards,
-- 
Krzysztof Kozlowski <krzk@kernel.org>

Re: (subset) [PATCH v3 0/6] Add minimal Exynos8855 SoC support

[Krzysztof Kozlowski]

On Sat, 27 Jun 2026 22:42:22 +0530, Alim Akhtar wrote:
> This series adds initial support for the Exynos8855 SoC and also
> initial SMDK board support.
> 
> Exynos8855 is octa-core CPUs, a combination of Cortex-A720 and Cortex-A520,
> arranged in 3 clusters. And other peripheral for mobile application.
> 
> This initial support consists of CPUs, pinctrl and related nodes
> needed for initial kernel boot.
> 
> [...]

Applied, thanks!

[1/6] dt-binding: ARM: samsung: Add Samsung Exynos8855
      https://git.kernel.org/krzk/linux/c/4b4a2ce19af5badef165c109d0d6d9f7c102914a
[5/6] arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk
      https://git.kernel.org/krzk/linux/c/f03058d3768c3ec4af0fab7a36d0631423cb3cf5
[6/6] MAINTAINERS: Add entry for Samsung Exynos8855 SoC
      https://git.kernel.org/krzk/linux/c/a87d503a0ab077b0d9892290ab7dbec29f922eb1

Best regards,
-- 
Krzysztof Kozlowski <krzk@kernel.org>