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From: Jie Gan <jie.gan@oss.qualcomm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mike Leach <mike.leach@linaro.org>,
	James Clark <james.clark@linaro.org>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Tingwei Zhang <tingwei.zhang@oss.qualcomm.com>,
	Mao Jinlong <jinlong.mao@oss.qualcomm.com>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	devicetree@vger.kernel.org, Krzysztof Kozlowski <krzk@kernel.org>
Subject: Re: [PATCH v10 5/8] dt-bindings: arm: add an interrupt property for Coresight CTCU
Date: Tue, 27 Jan 2026 08:59:33 +0800	[thread overview]
Message-ID: <49e38ec0-3ad8-4808-9488-46d444a52211@oss.qualcomm.com> (raw)
In-Reply-To: <cd175b3d-d8d1-4efd-9698-80a6c238d819@arm.com>



On 1/27/2026 1:22 AM, Suzuki K Poulose wrote:
> On 22/01/2026 02:08, Jie Gan wrote:
>> Add an interrupt property to CTCU device. The interrupt will be triggered
>> when the data size in the ETR buffer exceeds the threshold of the
>> BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register
>> of CTCU device will enable the interrupt.
>>
>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Reviewed-by: Mike Leach <mike.leach@linaro.org>
>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> ---
>>   Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 10 
>> ++++++++++
>>   1 file changed, 10 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight- 
>> ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight- 
>> ctcu.yaml
>> index c969c16c21ef..ac27a8b89085 100644
>> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>> @@ -39,6 +39,11 @@ properties:
>>       items:
>>         - const: apb
>> +  interrupts:
>> +    items:
>> +      - description: Interrupt for the ETR device connected to in-port0.
>> +      - description: Interrupt for the ETR device connected to in-port1.
> 
> Is this all the hardware supports ? i.e., can it only have two ports 
> ever ? If not, why restrict it to two ?
> 

The maximum number of the TMC ETR devices of the existed QCOM platforms 
is 2. Per Krzysztof's suggestion in the earlier version, I limited the 
port number to [0..1], so as well as the interrupts.

Thanks,
Jie


> Suzuki
> 
> 
>> +
>>     label:
>>       description:
>>         Description of a coresight device.
>> @@ -60,6 +65,8 @@ additionalProperties: false
>>   examples:
>>     - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>>       ctcu@1001000 {
>>           compatible = "qcom,sa8775p-ctcu";
>>           reg = <0x1001000 0x1000>;
>> @@ -67,6 +74,9 @@ examples:
>>           clocks = <&aoss_qmp>;
>>           clock-names = "apb";
>> +        interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
>> +                     <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>;
>> +
>>           in-ports {
>>               #address-cells = <1>;
>>               #size-cells = <0>;
>>
> 


  reply	other threads:[~2026-01-27  0:59 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-22  2:08 [PATCH v10 0/8] coresight: ctcu: Enable byte-cntr function for TMC ETR Jie Gan
2026-01-22  2:08 ` [PATCH v10 1/8] coresight: core: Refactoring ctcu_get_active_port and make it generic Jie Gan
2026-01-22 10:00   ` Suzuki K Poulose
2026-01-23  1:27     ` Jie Gan
2026-01-22  2:08 ` [PATCH v10 2/8] coresight: tmc: add create/clean functions for etr_buf_list Jie Gan
2026-01-22  2:08 ` [PATCH v10 3/8] coresight: tmc: Introduce sysfs_read_ops to wrap sysfs read operations Jie Gan
2026-01-22 10:07   ` Suzuki K Poulose
2026-01-23  1:32     ` Jie Gan
2026-01-22  2:08 ` [PATCH v10 4/8] coresight: etr: refactor the tmc_etr_get_catu_device function Jie Gan
2026-01-26 16:10   ` Suzuki K Poulose
2026-01-27  1:00     ` Jie Gan
2026-01-22  2:08 ` [PATCH v10 5/8] dt-bindings: arm: add an interrupt property for Coresight CTCU Jie Gan
2026-01-26 17:22   ` Suzuki K Poulose
2026-01-27  0:59     ` Jie Gan [this message]
2026-01-22  2:08 ` [PATCH v10 6/8] coresight: ctcu: enable byte-cntr for TMC ETR devices Jie Gan
2026-01-22  2:08 ` [PATCH v10 7/8] coresight: tmc: integrate byte-cntr's read_ops with sysfs file_ops Jie Gan
2026-01-22  2:08 ` [PATCH v10 8/8] arm64: dts: qcom: lemans: add interrupts to CTCU device Jie Gan

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