Re: [tip:perfcounters/urgent] x86: atomic64: The atomic64_t data type should be 8 bytes aligned on 32-bit too

["H. Peter Anvin" <hpa@zytor.com>]

Linus Torvalds wrote:
> 
> It's not necessarily even about "two cachelines". It's true that crossing 
> cachelines is extra painful, but from a CPU core angle, there's another 
> access width that matters almost as much, namely the width of the bus 
> between the core and the L1 cache. If it's not aligned to that, the core 
> needs to do each 8-byte read/write as two accesses, even if it's to the 
> same cacheline, and that complicates things.
> 
> The cacheline itself is generally larger than the cache access width. I 
> could easily see a 64B cacheline, but a 256b (32B) bus between the cache 
> and the core.
> 
> Making the atomics be naturally aligned means that you never cross either 
> one, of course.
> 

Sometimes, of course, that down-mux is where alignment happens, too.
Either which way, I don't think there is any doubt that unaligned
atomics are just asking for trouble.

	-hpa

-- 
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.