From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
To: Ming Lei <tom.leiming@gmail.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org,
Greg KH <greg@kroah.com>,
Matthew Dharm <mdharm-kernel@one-eyed-alien.net>
Subject: Re: [PATCH] isp1760: Flush the D-cache for the pipe-in transfer buffers
Date: Tue, 02 Feb 2010 16:54:22 +0100 [thread overview]
Message-ID: <4B684AAE.9020609@linutronix.de> (raw)
In-Reply-To: <d82e647a1002020741n4a048395o6ebf7ffaf8457819@mail.gmail.com>
Ming Lei wrote:
> 2010/2/2 Catalin Marinas <catalin.marinas@arm.com>:
>
>> + if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) == PIPE_BULK) {
>> + void *ptr;
>> + for (ptr = urb->transfer_buffer;
>> + ptr < urb->transfer_buffer + urb->transfer_buffer_length;
>> + ptr += PAGE_SIZE)
>> + flush_dcache_page(virt_to_page(ptr));
>
> If the page is mapped into highmem, seems virt_to_page doesn't work well.
This does not matter because this can not happen :). If the buffer is
highmem then a bounce buffer is used. See commit 96983d2d8 aka "USB:
storage: set bounce limit for non-DMA-capable host controllers"
Sebastian
prev parent reply other threads:[~2010-02-02 15:54 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-02-02 11:11 Catalin Marinas
2010-02-02 12:08 ` Sebastian Andrzej Siewior
2010-02-02 15:28 ` Catalin Marinas
2010-02-02 15:41 ` Ming Lei
2010-02-02 15:54 ` Catalin Marinas
2010-02-02 15:54 ` Sebastian Andrzej Siewior [this message]
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