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From: Jiri Slaby <jirislaby@gmail.com>
To: Borislav Petkov <bp@amd64.org>
Cc: "H. Peter Anvin" <hpa@zytor.com>,
	"x86@kernel.org" <x86@kernel.org>,
	Linux kernel mailing list <linux-kernel@vger.kernel.org>
Subject: Re: intel_cacheinfo: potential NULL dereference?
Date: Tue, 22 Jun 2010 16:11:04 +0200	[thread overview]
Message-ID: <4C20C478.9030505@gmail.com> (raw)
In-Reply-To: <20100622130825.GB27658@aftab>

On 06/22/2010 03:08 PM, Borislav Petkov wrote:
> From: Jiri Slaby <jirislaby@gmail.com>
> Date: Tue, Jun 22, 2010 at 07:20:14AM -0400
> 
>> On 06/22/2010 01:18 PM, Jiri Slaby wrote:
>>> Stanse found, that this_leaf->l3 is dereferenced at <<1>>, but checked
>>> for being NULL at <<2>>. Is the check superfluous or the dev assignment
>>> should go after the check?
>>
>> Oh, and I have another report with same symptoms for show_cache_disable.
> 
> Right, so I have a patch in tip/x86/cpu
> (8cc1176e5de534d55cb26ff0cef3fd0d6ad8c3c0) which reorganizes
> and cleans up that code. With it, all possible checks land in
> amd_check_l3_disable() and if they have all been passed, the PCI dev is
> guaranteed to be properly set. So no need for sprinkling additional NULL
> checks in the code.
> 
> How's that?

Looks good.

thanks,
-- 
js

  reply	other threads:[~2010-06-22 14:11 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-06-22 11:18 Jiri Slaby
2010-06-22 11:20 ` Jiri Slaby
2010-06-22 13:08   ` Borislav Petkov
2010-06-22 14:11     ` Jiri Slaby [this message]
2010-06-22 17:09       ` H. Peter Anvin
2010-06-22 19:19         ` Borislav Petkov
2010-06-22 19:45           ` [PATCH -v2] x86, cacheinfo: Carve out L3 cache slot accessors Borislav Petkov
2010-06-22 15:15   ` intel_cacheinfo: potential NULL dereference? H. Peter Anvin

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