* [PATCH] spi_topcliff_pch: supports a spi mode setup and bit order setup by IO control
@ 2011-07-20 5:56 Toshiharu Okada
2011-08-04 0:20 ` Toshiharu Okada
2011-10-06 5:24 ` Tomoya MORINAGA
0 siblings, 2 replies; 3+ messages in thread
From: Toshiharu Okada @ 2011-07-20 5:56 UTC (permalink / raw)
To: grant.likely, spi-devel-general, linux-kernel
Cc: qi.wang, yong.y.wang, joel.clark, kok.howg.ewe, tomoya-linux,
Toshiharu Okada
This patch supports a spi mode setup and bit order setup by IO control.
spi mode: mode 0 to mode 3
bit order: LSB first, MSB first
Signed-off-by: Toshiharu Okada <toshiharu-linux@dsn.okisemi.com>
---
drivers/spi/spi_topcliff_pch.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/spi_topcliff_pch.c b/drivers/spi/spi_topcliff_pch.c
index 79e48d4..dec83c9 100644
--- a/drivers/spi/spi_topcliff_pch.c
+++ b/drivers/spi/spi_topcliff_pch.c
@@ -1038,6 +1038,7 @@ static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
master->num_chipselect = PCH_MAX_CS;
master->setup = pch_spi_setup;
master->transfer = pch_spi_transfer;
+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
dev_dbg(&pdev->dev,
"%s transfer member of SPI master initialized\n", __func__);
--
1.7.4.4
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] spi_topcliff_pch: supports a spi mode setup and bit order setup by IO control
2011-07-20 5:56 [PATCH] spi_topcliff_pch: supports a spi mode setup and bit order setup by IO control Toshiharu Okada
@ 2011-08-04 0:20 ` Toshiharu Okada
2011-10-06 5:24 ` Tomoya MORINAGA
1 sibling, 0 replies; 3+ messages in thread
From: Toshiharu Okada @ 2011-08-04 0:20 UTC (permalink / raw)
To: Toshiharu Okada, grant.likely, spi-devel-general, linux-kernel
Cc: qi.wang, yong.y.wang, joel.clark, kok.howg.ewe, tomoya-linux
Hi Grant,
Could you review this patch?
Thanks in advance.
Best Regards
Toshiharu Okada
----- Original Message -----
Sent: Wednesday, July 20, 2011 2:56 PM
Subject: [PATCH] spi_topcliff_pch: supports a spi mode setup and bit order
setup by IO control
This patch supports a spi mode setup and bit order setup by IO control.
spi mode: mode 0 to mode 3
bit order: LSB first, MSB first
Signed-off-by: Toshiharu Okada <toshiharu-linux@dsn.okisemi.com>
---
drivers/spi/spi_topcliff_pch.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/spi_topcliff_pch.c b/drivers/spi/spi_topcliff_pch.c
index 79e48d4..dec83c9 100644
--- a/drivers/spi/spi_topcliff_pch.c
+++ b/drivers/spi/spi_topcliff_pch.c
@@ -1038,6 +1038,7 @@ static int pch_spi_probe(struct pci_dev *pdev, const
struct pci_device_id *id)
master->num_chipselect = PCH_MAX_CS;
master->setup = pch_spi_setup;
master->transfer = pch_spi_transfer;
+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
dev_dbg(&pdev->dev,
"%s transfer member of SPI master initialized\n", __func__);
--
1.7.4.4
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] spi_topcliff_pch: supports a spi mode setup and bit order setup by IO control
2011-07-20 5:56 [PATCH] spi_topcliff_pch: supports a spi mode setup and bit order setup by IO control Toshiharu Okada
2011-08-04 0:20 ` Toshiharu Okada
@ 2011-10-06 5:24 ` Tomoya MORINAGA
1 sibling, 0 replies; 3+ messages in thread
From: Tomoya MORINAGA @ 2011-10-06 5:24 UTC (permalink / raw)
To: Toshiharu Okada
Cc: grant.likely, spi-devel-general, linux-kernel, qi.wang,
yong.y.wang, joel.clark, kok.howg.ewe, tomoya-linux
Hi Grant,
It seems this patch Toshiharu posted in 20-July remains not to be
reviewed by you.
Could you review this patch and merge to your tree ?
Thanks in advance,
--
tomoya
ROHM Co., Ltd.
(2011/07/20 14:56), Toshiharu Okada wrote:
> This patch supports a spi mode setup and bit order setup by IO control.
> spi mode: mode 0 to mode 3
> bit order: LSB first, MSB first
>
> Signed-off-by: Toshiharu Okada<toshiharu-linux@dsn.okisemi.com>
> ---
> drivers/spi/spi_topcliff_pch.c | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/spi/spi_topcliff_pch.c b/drivers/spi/spi_topcliff_pch.c
> index 79e48d4..dec83c9 100644
> --- a/drivers/spi/spi_topcliff_pch.c
> +++ b/drivers/spi/spi_topcliff_pch.c
> @@ -1038,6 +1038,7 @@ static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> master->num_chipselect = PCH_MAX_CS;
> master->setup = pch_spi_setup;
> master->transfer = pch_spi_transfer;
> + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
> dev_dbg(&pdev->dev,
> "%s transfer member of SPI master initialized\n", __func__);
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2011-10-06 5:24 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2011-07-20 5:56 [PATCH] spi_topcliff_pch: supports a spi mode setup and bit order setup by IO control Toshiharu Okada
2011-08-04 0:20 ` Toshiharu Okada
2011-10-06 5:24 ` Tomoya MORINAGA
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