Re: [PATCH v8 2/9] clk: qcom: gcc-msm8939: mark Venus core GDSCs as hardware controlled

[Taniya Das <taniya.das@oss.qualcomm.com>]

On 5/26/2026 4:20 AM, Bryan O'Donoghue wrote:
> On 25/05/2026 10:56, Erikas Bitovtas wrote:
>> +    for (; i < res->vcodec_pmdomains_num; i++) {
>> +        pd_dev = core->pmdomains->pd_devs[i];
>> +        ret = pm_runtime_resume_and_get(pd_dev);
>> +        if (ret)
>> +            goto err;
>> +
>> +        ret = dev_pm_genpd_set_hwmode(pd_dev, true);
>> +        if (ret && ret != -EOPNOTSUPP) {
>> +            pm_runtime_put_sync(pd_dev);
>> +            goto err;
>> +        }
>> +    }
> 
> In Iris we do
> 
> - enable_power_domains
> - enable_clocks
> - set hwmode
> 

This sequence will always ensure clock can be polled as the GDSC is
still in SW mode.


> Instead of
> 
> - enable_power_domains
> - set hwmode
> - enable clocks
> 

This sequence will require the clock to have SKIP or DELAY as the GDSC
is moved to HW mode and it is not guaranteed to match the SW expectation.


-- 
Thanks,
Taniya Das