From: Daniel Lezcano <daniel.lezcano@linaro.org>
To: Ley Foon Tan <leyfoon.tan@starfivetech.com>,
Thomas Gleixner <tglx@linutronix.de>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: atishp@rivosinc.com, Samuel Holland <samuel.holland@sifive.com>,
Anup Patel <apatel@ventanamicro.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Ley Foon Tan <lftan.linux@gmail.com>,
stable@vger.kernel.org
Subject: Re: [PATCH v3] clocksource: timer-riscv: Clear timer interrupt on timer initialization
Date: Wed, 13 Mar 2024 12:11:26 +0100 [thread overview]
Message-ID: <4ac22b8b-9230-4489-8b38-a2ba79c16d16@linaro.org> (raw)
In-Reply-To: <20240306172330.255844-1-leyfoon.tan@starfivetech.com>
On 06/03/2024 18:23, Ley Foon Tan wrote:
> In the RISC-V specification, the stimecmp register doesn't have a default
> value. To prevent the timer interrupt from being triggered during timer
> initialization, clear the timer interrupt by writing stimecmp with a
> maximum value.
>
> Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available")
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
>
> ---
Applied, thanks
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next prev parent reply other threads:[~2024-03-13 11:11 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-06 17:23 Ley Foon Tan
2024-03-12 17:40 ` Samuel Holland
2024-03-12 19:08 ` Atish Kumar Patra
2024-03-13 11:11 ` Daniel Lezcano [this message]
2024-03-18 10:07 ` [tip: timers/core] clocksource/drivers/timer-riscv: " tip-bot2 for Ley Foon Tan
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