From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Sibi Sankar <sibi.sankar@oss.qualcomm.com>,
Pankaj Patil <pankaj.patil@oss.qualcomm.com>
Cc: Rajendra Nayak <rajendra.nayak@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/5] arm64: dts: qcom: Add Kalambo SoC
Date: Thu, 23 Jul 2026 14:29:21 +0200 [thread overview]
Message-ID: <4afe6c0f-23e6-4081-84ac-67d43ced6aed@oss.qualcomm.com> (raw)
In-Reply-To: <20260722-b4-kalambo-crd-v2-2-32d4addc1ac9@oss.qualcomm.com>
On 7/22/26 12:55 PM, Gopikrishna Garmidi wrote:
> Introduce support for the Qualcomm Kalambo SoC. It is derived from Mahua
> with CPU cluster 0 removed, leaving it with just cluster 1 (cpu6-cpu11).
>
> - The surviving cluster is re-added to the cpu-map as cluster0, since the
> kernel's cpu-map cluster scan stops at the first missing "clusterN"
> index.
>
> - cpu6-cpu11 are reassigned to SCMI performance domain 0, as domain 1
> (the former cluster 0) is no longer present.
>
> - Point the SCMI transport at the SRAM and mailbox addresses used by
> the Kalambo SCP firmware, which differ from those inherited from
> Glymur.
>
> Add labels to the Glymur cpu-map and its cluster nodes to allow their
> removal and override on derived SoCs.
>
> Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
> ---
[...]
> @@ -274,8 +274,8 @@ cpu17: cpu@20500 {
> #cooling-cells = <2>;
> };
>
> - cpu-map {
> - cluster0 {
> + cpu_map: cpu-map {
> + cpu_map_cluster0: cluster0 {
> core0 {
> cpu = <&cpu0>;
> };
> @@ -301,7 +301,7 @@ core5 {
> };
> };
>
> - cluster1 {
> + cpu_map_cluster1: cluster1 {
The deletes are recursive, so if you just delete the whole map,
you don't need to delete the children (and can drop the labels)
You can then add a label to /cpus and reference it, redefining the
map in kalambo.dtsi
[...]
> +&imem {
> + reg = <0x0 0x81e08600 0x0 0x380>;
> + ranges = <0x0 0x0 0x81e08600 0x380>;
Is the size *actually* different between the SoCs?
> + cpu_scp_lpri1: scp-sram-section@200 {
> + compatible = "arm,scmi-shmem";
> + reg = <0x200 0x180>;
> + };
With this shifted, is cpu_scp_lpri0 still at the same base?
> +};
> +
> +&pdp0_mbox {
> + reg = <0 0x17610000 0 0x8000>, <0 0x1a980000 0 0x8000>;
Please keep one entry per line and use '0x0' instead of '0'
Konrad
next prev parent reply other threads:[~2026-07-23 12:29 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-22 10:55 [PATCH v2 0/5] arm64: dts: qcom: Add Kalambo SoC and CRD Gopikrishna Garmidi
2026-07-22 10:55 ` [PATCH v2 1/5] dt-bindings: arm: qcom: Document Kalambo SoC and board Gopikrishna Garmidi
2026-07-22 10:55 ` [PATCH v2 2/5] arm64: dts: qcom: Add Kalambo SoC Gopikrishna Garmidi
2026-07-23 12:29 ` Konrad Dybcio [this message]
2026-07-24 11:51 ` Gopikrishna Garmidi
2026-07-22 10:55 ` [PATCH v2 3/5] arm64: dts: qcom: Add Kalambo CRD Gopikrishna Garmidi
2026-07-22 13:05 ` Dmitry Baryshkov
2026-07-22 10:55 ` [PATCH v2 4/5] firmware: qcom: scm: Allow QSEECOM on " Gopikrishna Garmidi
2026-07-22 10:55 ` [PATCH v2 5/5] soc: qcom: ubwc: Add Kalambo UBWC config Gopikrishna Garmidi
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