Re: [PATCH v2 2/5] arm64: dts: qcom: Add Kalambo SoC

[Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>]

On 7/23/2026 5:59 PM, Konrad Dybcio wrote:
> On 7/22/26 12:55 PM, Gopikrishna Garmidi wrote:
>> Introduce support for the Qualcomm Kalambo SoC. It is derived from Mahua
>> with CPU cluster 0 removed, leaving it with just cluster 1 (cpu6-cpu11).
>>
>>   - The surviving cluster is re-added to the cpu-map as cluster0, since the
>>     kernel's cpu-map cluster scan stops at the first missing "clusterN"
>>     index.
>>
>>   - cpu6-cpu11 are reassigned to SCMI performance domain 0, as domain 1
>>     (the former cluster 0) is no longer present.
>>
>>   - Point the SCMI transport at the SRAM and mailbox addresses used by
>>     the Kalambo SCP firmware, which differ from those inherited from
>>     Glymur.
>>
>> Add labels to the Glymur cpu-map and its cluster nodes to allow their
>> removal and override on derived SoCs.
>>
>> Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
>> ---
> 
> [...]
> 
>> @@ -274,8 +274,8 @@ cpu17: cpu@20500 {
>>   			#cooling-cells = <2>;
>>   		};
>>   
>> -		cpu-map {
>> -			cluster0 {
>> +		cpu_map: cpu-map {
>> +			cpu_map_cluster0: cluster0 {
>>   				core0 {
>>   					cpu = <&cpu0>;
>>   				};
>> @@ -301,7 +301,7 @@ core5 {
>>   				};
>>   			};
>>   
>> -			cluster1 {
>> +			cpu_map_cluster1: cluster1 {
> 
> The deletes are recursive, so if you just delete the whole map,
> you don't need to delete the children (and can drop the labels)
> 
> You can then add a label to /cpus and reference it, redefining the
> map in kalambo.dtsi
> 
> [...]
> 

ACK, will drop child labels and do a full cpu-map delete + override in 
kalambo.dtsi.

>> +&imem {
>> +	reg = <0x0 0x81e08600 0x0 0x380>;
>> +	ranges = <0x0 0x0 0x81e08600 0x380>;
> 
> Is the size *actually* different between the SoCs?
>

Yes. Kalambo uses PDP1, its tx shmem (lpri1) sits at offset 0x200
vs 0x180 on Glymur (PDP0). That 0x80 shift pushes the tx region end
to 0x380, requiring the imem size override. Increasing Glymur's size
would cause a crash, so this stays as a Kalambo-only override.

>> +	cpu_scp_lpri1: scp-sram-section@200 {
>> +		compatible = "arm,scmi-shmem";
>> +		reg = <0x200 0x180>;
>> +	};
> 
> With this shifted, is cpu_scp_lpri0 still at the same base?
> 

Yes, lpri0 (rx) is shared and stays at offset 0x0. Only lpri1 (tx)
shifts.

>> +};
>> +
>> +&pdp0_mbox {
>> +	reg = <0 0x17610000 0 0x8000>, <0 0x1a980000 0 0x8000>;
> 
> Please keep one entry per line and use '0x0' instead of '0'

ACK, will reformat as:
	reg = <0x0 0x17610000 0x0 0x8000>,
	      <0x0 0x1a980000 0x0 0x8000>;


Thanks,
Gopikrishna