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From: Icenowy Zheng <uwu@icenowy.me>
To: Paul Kocialkowski <paulk@sys-base.io>,
	linux-media@vger.kernel.org,  devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	 linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
	 linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org,
	 linux-gpio@vger.kernel.org
Cc: Yong Deng <yong.deng@magewell.com>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	Samuel Holland <samuel@sholland.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Maxime Ripard <mripard@kernel.org>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	 David Airlie <airlied@gmail.com>,
	Simona Vetter <simona@ffwll.ch>,
	Linus Walleij <linus.walleij@linaro.org>,
	 Icenowy Zheng <icenowy@aosc.xyz>,
	Andre Przywara <andre.przywara@arm.com>
Subject: Re: [PATCH 5/5] drm/sun4i: Run the mixer clock at 297 MHz on V3s
Date: Wed, 02 Jul 2025 10:52:10 +0800	[thread overview]
Message-ID: <4bc1c1fd9aa1e97a04d964fc5601155ade52cd2d.camel@icenowy.me> (raw)
In-Reply-To: <20250701201124.812882-6-paulk@sys-base.io>

在 2025-07-01星期二的 22:11 +0200,Paul Kocialkowski写道:
> The DE mixer clock is currently set to run at 150 MHz, while the
> Allwinner BSP configures it at 300 MHz and other platforms typically
> run at 297 MHz.
> 
> 150 MHz appears to be enough given the restricted graphics
> capabilities
> of the SoC (with a work area of only 1024x1024). However it typically
> causes the DE clock to be parented to the periph0 pll instead of the
> video PLL.
> 
> While this should generally not be a concern, it appears (based on
> experimentation) that both the DE and TCON clocks need to be parented
> to the same PLL for these units to work. While we cannot represent
> this
> constraint in the clock driver, it appears that the TCON clock will
> often get parented to the video pll (typically running at 297 MHz for

Ah I think pixel clocks are arbitary and nothing could be predicted
about it...

> the CSI units needs), for instance when driving displays with a 33
> MHz
> pixel clock (33 being a natural divider of 297).
> 
> Running the DE clock at 297 MHz will typically result in parenting to
> the video pll instead of the periph0 pll, thus making the display
> output functional.
> 
> This is all a bit fragile but it solves the issue with displays
> running
> at 33 Mhz and brings V3s to use the same frequency as other
> platforms,
> making support more unified.
> 
> Also align and sort the fields of the v3s mixer config while at it.
> 
> Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> ---
>  drivers/gpu/drm/sun4i/sun8i_mixer.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
> b/drivers/gpu/drm/sun4i/sun8i_mixer.c
> index 8b41d33baa30..35fdc2451060 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
> +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
> @@ -670,12 +670,12 @@ static const struct sun8i_mixer_cfg
> sun8i_r40_mixer1_cfg = {
>  };
>  
>  static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
> -       .vi_num = 2,
> -       .ui_num = 1,
> -       .scaler_mask = 0x3,
> -       .scanline_yuv = 2048,
> -       .ccsc = CCSC_MIXER0_LAYOUT,
> -       .mod_rate = 150000000,
> +       .ccsc           = CCSC_MIXER0_LAYOUT,
> +       .mod_rate       = 297000000,
> +       .scaler_mask    = 0x3,
> +       .scanline_yuv   = 2048,
> +       .ui_num         = 1,
> +       .vi_num         = 2,
>  };
>  
>  static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = {


  reply	other threads:[~2025-07-02  2:53 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-01 20:11 [PATCH 0/5] sunxi: Various minor V3s clock/pinctrl fixes Paul Kocialkowski
2025-07-01 20:11 ` [PATCH 1/5] pinctrl: sunxi: v3s: Fix wrong comment about UART2 pinmux Paul Kocialkowski
2025-07-02  3:04   ` Icenowy Zheng
2025-07-02  7:21   ` Chen-Yu Tsai
2025-07-04  8:01   ` Linus Walleij
2025-07-01 20:11 ` [PATCH 2/5] clk: sunxi-ng: v3s: Fix CSI SCLK clock name Paul Kocialkowski
2025-07-02  3:08   ` Icenowy Zheng
2025-07-01 20:11 ` [PATCH 3/5] clk: sunxi-ng: v3s: Fix CSI1 MCLK " Paul Kocialkowski
2025-07-02  3:10   ` Icenowy Zheng
2025-07-01 20:11 ` [PATCH 4/5] clk: sunxi-ng: v3s: Fix TCON clock parents Paul Kocialkowski
2025-07-01 20:11 ` [PATCH 5/5] drm/sun4i: Run the mixer clock at 297 MHz on V3s Paul Kocialkowski
2025-07-02  2:52   ` Icenowy Zheng [this message]
2025-07-02 11:36   ` Maxime Ripard
2025-07-02 12:15     ` Paul Kocialkowski
2025-07-03 15:37 ` (subset) [PATCH 0/5] sunxi: Various minor V3s clock/pinctrl fixes Chen-Yu Tsai

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