* [PATCH v2 1/7] ARM: dts: lan966x: swap dma channels for crypto node
2022-03-04 15:35 [PATCH v2 0/7] ARM: dts: lan966x: dtsi improvements and KSwitch D10 support Michael Walle
@ 2022-03-04 15:35 ` Michael Walle
2022-03-04 15:35 ` [PATCH v2 2/7] ARM: dts: lan966x: add sgpio node Michael Walle
` (5 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Michael Walle @ 2022-03-04 15:35 UTC (permalink / raw)
To: Kavyasree Kotagiri, Nicolas Ferre
Cc: Arnd Bergmann, Olof Johansson, soc, linux-arm-kernel, devicetree,
linux-kernel, Rob Herring, Krzysztof Kozlowski,
Alexandre Belloni, Claudiu Beznea, Michael Walle
The YAML binding (crypto/atmel,at91sam9g46-aes.yaml) mandates the order
of the channels. Swap them to pass devicetree validation.
Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port board pcb8291")
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
arch/arm/boot/dts/lan966x.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index 7d2869648050..5e9cbc8cdcbc 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -114,9 +114,9 @@ aes: crypto@e004c000 {
compatible = "atmel,at91sam9g46-aes";
reg = <0xe004c000 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>,
- <&dma0 AT91_XDMAC_DT_PERID(12)>;
- dma-names = "rx", "tx";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>,
+ <&dma0 AT91_XDMAC_DT_PERID(13)>;
+ dma-names = "tx", "rx";
clocks = <&nic_clk>;
clock-names = "aes_clk";
};
--
2.30.2
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v2 2/7] ARM: dts: lan966x: add sgpio node
2022-03-04 15:35 [PATCH v2 0/7] ARM: dts: lan966x: dtsi improvements and KSwitch D10 support Michael Walle
2022-03-04 15:35 ` [PATCH v2 1/7] ARM: dts: lan966x: swap dma channels for crypto node Michael Walle
@ 2022-03-04 15:35 ` Michael Walle
2022-03-30 13:25 ` Claudiu.Beznea
2022-03-04 15:35 ` [PATCH v2 3/7] ARM: dts: lan966x: add missing uart DMA channel Michael Walle
` (4 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Michael Walle @ 2022-03-04 15:35 UTC (permalink / raw)
To: Kavyasree Kotagiri, Nicolas Ferre
Cc: Arnd Bergmann, Olof Johansson, soc, linux-arm-kernel, devicetree,
linux-kernel, Rob Herring, Krzysztof Kozlowski,
Alexandre Belloni, Claudiu Beznea, Michael Walle
Add the device tree node for the SGPIO IP block reused from the
SparX-5. Keep the node disabled by default.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/boot/dts/lan966x.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index 5e9cbc8cdcbc..39dfdb8e29ed 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -223,6 +223,32 @@ gpio: pinctrl@e2004064 {
#interrupt-cells = <2>;
};
+ sgpio: gpio@e2004190 {
+ compatible = "microchip,sparx5-sgpio";
+ reg = <0xe2004190 0x118>;
+ clocks = <&sys_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgpio_in: gpio@0 {
+ compatible = "microchip,sparx5-sgpio-bank";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ sgpio_out: gpio@1 {
+ compatible = "microchip,sparx5-sgpio-bank";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ };
+ };
+
gic: interrupt-controller@e8c11000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
#interrupt-cells = <3>;
--
2.30.2
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v2 2/7] ARM: dts: lan966x: add sgpio node
2022-03-04 15:35 ` [PATCH v2 2/7] ARM: dts: lan966x: add sgpio node Michael Walle
@ 2022-03-30 13:25 ` Claudiu.Beznea
0 siblings, 0 replies; 13+ messages in thread
From: Claudiu.Beznea @ 2022-03-30 13:25 UTC (permalink / raw)
To: michael, Kavyasree.Kotagiri, Nicolas.Ferre
Cc: arnd, olof, soc, linux-arm-kernel, devicetree, linux-kernel,
robh+dt, krzysztof.kozlowski, alexandre.belloni
On 04.03.2022 17:35, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add the device tree node for the SGPIO IP block reused from the
> SparX-5. Keep the node disabled by default.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
> arch/arm/boot/dts/lan966x.dtsi | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index 5e9cbc8cdcbc..39dfdb8e29ed 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -223,6 +223,32 @@ gpio: pinctrl@e2004064 {
> #interrupt-cells = <2>;
> };
>
> + sgpio: gpio@e2004190 {
> + compatible = "microchip,sparx5-sgpio";
> + reg = <0xe2004190 0x118>;
> + clocks = <&sys_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + sgpio_in: gpio@0 {
> + compatible = "microchip,sparx5-sgpio-bank";
> + reg = <0>;
> + gpio-controller;
> + #gpio-cells = <3>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + };
> +
> + sgpio_out: gpio@1 {
> + compatible = "microchip,sparx5-sgpio-bank";
> + reg = <1>;
> + gpio-controller;
> + #gpio-cells = <3>;
> + };
> + };
> +
> gic: interrupt-controller@e8c11000 {
> compatible = "arm,gic-400", "arm,cortex-a7-gic";
> #interrupt-cells = <3>;
> --
> 2.30.2
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 3/7] ARM: dts: lan966x: add missing uart DMA channel
2022-03-04 15:35 [PATCH v2 0/7] ARM: dts: lan966x: dtsi improvements and KSwitch D10 support Michael Walle
2022-03-04 15:35 ` [PATCH v2 1/7] ARM: dts: lan966x: swap dma channels for crypto node Michael Walle
2022-03-04 15:35 ` [PATCH v2 2/7] ARM: dts: lan966x: add sgpio node Michael Walle
@ 2022-03-04 15:35 ` Michael Walle
2022-03-30 13:25 ` Claudiu.Beznea
2022-03-04 15:35 ` [PATCH v2 4/7] ARM: dts: lan966x: add all flexcom usart nodes Michael Walle
` (3 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Michael Walle @ 2022-03-04 15:35 UTC (permalink / raw)
To: Kavyasree Kotagiri, Nicolas Ferre
Cc: Arnd Bergmann, Olof Johansson, soc, linux-arm-kernel, devicetree,
linux-kernel, Rob Herring, Krzysztof Kozlowski,
Alexandre Belloni, Claudiu Beznea, Michael Walle
The usart node of the flexcom3 block is missing the DMA channels. Add
it.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/boot/dts/lan966x.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index 39dfdb8e29ed..230de3bdd5f1 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -144,6 +144,9 @@ usart3: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
+ <&dma0 AT91_XDMAC_DT_PERID(8)>;
+ dma-names = "tx", "rx";
clocks = <&nic_clk>;
clock-names = "usart";
atmel,fifo-size = <32>;
--
2.30.2
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v2 3/7] ARM: dts: lan966x: add missing uart DMA channel
2022-03-04 15:35 ` [PATCH v2 3/7] ARM: dts: lan966x: add missing uart DMA channel Michael Walle
@ 2022-03-30 13:25 ` Claudiu.Beznea
0 siblings, 0 replies; 13+ messages in thread
From: Claudiu.Beznea @ 2022-03-30 13:25 UTC (permalink / raw)
To: michael, Kavyasree.Kotagiri, Nicolas.Ferre
Cc: arnd, olof, soc, linux-arm-kernel, devicetree, linux-kernel,
robh+dt, krzysztof.kozlowski, alexandre.belloni
On 04.03.2022 17:35, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> The usart node of the flexcom3 block is missing the DMA channels. Add
> it.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
> arch/arm/boot/dts/lan966x.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index 39dfdb8e29ed..230de3bdd5f1 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -144,6 +144,9 @@ usart3: serial@200 {
> compatible = "atmel,at91sam9260-usart";
> reg = <0x200 0x200>;
> interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
> + <&dma0 AT91_XDMAC_DT_PERID(8)>;
> + dma-names = "tx", "rx";
> clocks = <&nic_clk>;
> clock-names = "usart";
> atmel,fifo-size = <32>;
> --
> 2.30.2
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 4/7] ARM: dts: lan966x: add all flexcom usart nodes
2022-03-04 15:35 [PATCH v2 0/7] ARM: dts: lan966x: dtsi improvements and KSwitch D10 support Michael Walle
` (2 preceding siblings ...)
2022-03-04 15:35 ` [PATCH v2 3/7] ARM: dts: lan966x: add missing uart DMA channel Michael Walle
@ 2022-03-04 15:35 ` Michael Walle
2022-03-30 13:25 ` Claudiu.Beznea
2022-03-04 15:35 ` [PATCH v2 5/7] ARM: dts: lan966x: add flexcom SPI nodes Michael Walle
` (2 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Michael Walle @ 2022-03-04 15:35 UTC (permalink / raw)
To: Kavyasree Kotagiri, Nicolas Ferre
Cc: Arnd Bergmann, Olof Johansson, soc, linux-arm-kernel, devicetree,
linux-kernel, Rob Herring, Krzysztof Kozlowski,
Alexandre Belloni, Claudiu Beznea, Michael Walle
Add all the remaining usart nodes for the flexcom block. Although the
DMA channels are specified, DMA is not enabled by default because break
detection doesn't work with DMA.
Keep the nodes disabled by default.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/boot/dts/lan966x.dtsi | 52 ++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index 230de3bdd5f1..d7eacb0144f5 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -92,6 +92,19 @@ flx0: flexcom@e0040000 {
#size-cells = <1>;
ranges = <0x0 0xe0040000 0x800>;
status = "disabled";
+
+ usart0: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
+ <&dma0 AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
};
flx1: flexcom@e0044000 {
@@ -102,6 +115,19 @@ flx1: flexcom@e0044000 {
#size-cells = <1>;
ranges = <0x0 0xe0044000 0x800>;
status = "disabled";
+
+ usart1: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
+ <&dma0 AT91_XDMAC_DT_PERID(4)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
};
trng: rng@e0048000 {
@@ -129,6 +155,19 @@ flx2: flexcom@e0060000 {
#size-cells = <1>;
ranges = <0x0 0xe0060000 0x800>;
status = "disabled";
+
+ usart2: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
+ <&dma0 AT91_XDMAC_DT_PERID(6)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
};
flx3: flexcom@e0064000 {
@@ -181,6 +220,19 @@ flx4: flexcom@e0070000 {
#size-cells = <1>;
ranges = <0x0 0xe0070000 0x800>;
status = "disabled";
+
+ usart4: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
+ <&dma0 AT91_XDMAC_DT_PERID(10)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
};
timer0: timer@e008c000 {
--
2.30.2
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v2 4/7] ARM: dts: lan966x: add all flexcom usart nodes
2022-03-04 15:35 ` [PATCH v2 4/7] ARM: dts: lan966x: add all flexcom usart nodes Michael Walle
@ 2022-03-30 13:25 ` Claudiu.Beznea
0 siblings, 0 replies; 13+ messages in thread
From: Claudiu.Beznea @ 2022-03-30 13:25 UTC (permalink / raw)
To: michael, Kavyasree.Kotagiri, Nicolas.Ferre
Cc: arnd, olof, soc, linux-arm-kernel, devicetree, linux-kernel,
robh+dt, krzysztof.kozlowski, alexandre.belloni
On 04.03.2022 17:35, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add all the remaining usart nodes for the flexcom block. Although the
> DMA channels are specified, DMA is not enabled by default because break
> detection doesn't work with DMA.
>
> Keep the nodes disabled by default.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
> arch/arm/boot/dts/lan966x.dtsi | 52 ++++++++++++++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
>
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index 230de3bdd5f1..d7eacb0144f5 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -92,6 +92,19 @@ flx0: flexcom@e0040000 {
> #size-cells = <1>;
> ranges = <0x0 0xe0040000 0x800>;
> status = "disabled";
> +
> + usart0: serial@200 {
> + compatible = "atmel,at91sam9260-usart";
> + reg = <0x200 0x200>;
> + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
> + <&dma0 AT91_XDMAC_DT_PERID(2)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + clock-names = "usart";
> + atmel,fifo-size = <32>;
> + status = "disabled";
> + };
> };
>
> flx1: flexcom@e0044000 {
> @@ -102,6 +115,19 @@ flx1: flexcom@e0044000 {
> #size-cells = <1>;
> ranges = <0x0 0xe0044000 0x800>;
> status = "disabled";
> +
> + usart1: serial@200 {
> + compatible = "atmel,at91sam9260-usart";
> + reg = <0x200 0x200>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
> + <&dma0 AT91_XDMAC_DT_PERID(4)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + clock-names = "usart";
> + atmel,fifo-size = <32>;
> + status = "disabled";
> + };
> };
>
> trng: rng@e0048000 {
> @@ -129,6 +155,19 @@ flx2: flexcom@e0060000 {
> #size-cells = <1>;
> ranges = <0x0 0xe0060000 0x800>;
> status = "disabled";
> +
> + usart2: serial@200 {
> + compatible = "atmel,at91sam9260-usart";
> + reg = <0x200 0x200>;
> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
> + <&dma0 AT91_XDMAC_DT_PERID(6)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + clock-names = "usart";
> + atmel,fifo-size = <32>;
> + status = "disabled";
> + };
> };
>
> flx3: flexcom@e0064000 {
> @@ -181,6 +220,19 @@ flx4: flexcom@e0070000 {
> #size-cells = <1>;
> ranges = <0x0 0xe0070000 0x800>;
> status = "disabled";
> +
> + usart4: serial@200 {
> + compatible = "atmel,at91sam9260-usart";
> + reg = <0x200 0x200>;
> + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
> + <&dma0 AT91_XDMAC_DT_PERID(10)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + clock-names = "usart";
> + atmel,fifo-size = <32>;
> + status = "disabled";
> + };
> };
>
> timer0: timer@e008c000 {
> --
> 2.30.2
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 5/7] ARM: dts: lan966x: add flexcom SPI nodes
2022-03-04 15:35 [PATCH v2 0/7] ARM: dts: lan966x: dtsi improvements and KSwitch D10 support Michael Walle
` (3 preceding siblings ...)
2022-03-04 15:35 ` [PATCH v2 4/7] ARM: dts: lan966x: add all flexcom usart nodes Michael Walle
@ 2022-03-04 15:35 ` Michael Walle
2022-03-30 13:26 ` Claudiu.Beznea
2022-03-04 15:35 ` [PATCH v2 6/7] ARM: dts: lan966x: add flexcom I2C nodes Michael Walle
2022-03-04 15:35 ` [PATCH v2 7/7] ARM: dts: lan966x: add basic Kontron KSwitch D10 support Michael Walle
6 siblings, 1 reply; 13+ messages in thread
From: Michael Walle @ 2022-03-04 15:35 UTC (permalink / raw)
To: Kavyasree Kotagiri, Nicolas Ferre
Cc: Arnd Bergmann, Olof Johansson, soc, linux-arm-kernel, devicetree,
linux-kernel, Rob Herring, Krzysztof Kozlowski,
Alexandre Belloni, Claudiu Beznea, Michael Walle
Add all the SPI nodes for the flexcom IP block. Keep them
disabled by default.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/boot/dts/lan966x.dtsi | 75 ++++++++++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index d7eacb0144f5..a61d394ad04d 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -105,6 +105,21 @@ usart0: serial@200 {
atmel,fifo-size = <32>;
status = "disabled";
};
+
+ spi0: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
+ <&dma0 AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
flx1: flexcom@e0044000 {
@@ -128,6 +143,21 @@ usart1: serial@200 {
atmel,fifo-size = <32>;
status = "disabled";
};
+
+ spi1: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
+ <&dma0 AT91_XDMAC_DT_PERID(4)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
trng: rng@e0048000 {
@@ -168,6 +198,21 @@ usart2: serial@200 {
atmel,fifo-size = <32>;
status = "disabled";
};
+
+ spi2: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
+ <&dma0 AT91_XDMAC_DT_PERID(6)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
flx3: flexcom@e0064000 {
@@ -191,6 +236,21 @@ usart3: serial@200 {
atmel,fifo-size = <32>;
status = "disabled";
};
+
+ spi3: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
+ <&dma0 AT91_XDMAC_DT_PERID(8)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
dma0: dma-controller@e0068000 {
@@ -233,6 +293,21 @@ usart4: serial@200 {
atmel,fifo-size = <32>;
status = "disabled";
};
+
+ spi4: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
+ <&dma0 AT91_XDMAC_DT_PERID(10)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
timer0: timer@e008c000 {
--
2.30.2
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v2 5/7] ARM: dts: lan966x: add flexcom SPI nodes
2022-03-04 15:35 ` [PATCH v2 5/7] ARM: dts: lan966x: add flexcom SPI nodes Michael Walle
@ 2022-03-30 13:26 ` Claudiu.Beznea
0 siblings, 0 replies; 13+ messages in thread
From: Claudiu.Beznea @ 2022-03-30 13:26 UTC (permalink / raw)
To: michael, Kavyasree.Kotagiri, Nicolas.Ferre
Cc: arnd, olof, soc, linux-arm-kernel, devicetree, linux-kernel,
robh+dt, krzysztof.kozlowski, alexandre.belloni
On 04.03.2022 17:35, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add all the SPI nodes for the flexcom IP block. Keep them
> disabled by default.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
> arch/arm/boot/dts/lan966x.dtsi | 75 ++++++++++++++++++++++++++++++++++
> 1 file changed, 75 insertions(+)
>
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index d7eacb0144f5..a61d394ad04d 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -105,6 +105,21 @@ usart0: serial@200 {
> atmel,fifo-size = <32>;
> status = "disabled";
> };
> +
> + spi0: spi@400 {
> + compatible = "atmel,at91rm9200-spi";
> + reg = <0x400 0x200>;
> + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
> + <&dma0 AT91_XDMAC_DT_PERID(2)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + clock-names = "spi_clk";
> + atmel,fifo-size = <32>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> flx1: flexcom@e0044000 {
> @@ -128,6 +143,21 @@ usart1: serial@200 {
> atmel,fifo-size = <32>;
> status = "disabled";
> };
> +
> + spi1: spi@400 {
> + compatible = "atmel,at91rm9200-spi";
> + reg = <0x400 0x200>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
> + <&dma0 AT91_XDMAC_DT_PERID(4)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + clock-names = "spi_clk";
> + atmel,fifo-size = <32>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> trng: rng@e0048000 {
> @@ -168,6 +198,21 @@ usart2: serial@200 {
> atmel,fifo-size = <32>;
> status = "disabled";
> };
> +
> + spi2: spi@400 {
> + compatible = "atmel,at91rm9200-spi";
> + reg = <0x400 0x200>;
> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
> + <&dma0 AT91_XDMAC_DT_PERID(6)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + clock-names = "spi_clk";
> + atmel,fifo-size = <32>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> flx3: flexcom@e0064000 {
> @@ -191,6 +236,21 @@ usart3: serial@200 {
> atmel,fifo-size = <32>;
> status = "disabled";
> };
> +
> + spi3: spi@400 {
> + compatible = "atmel,at91rm9200-spi";
> + reg = <0x400 0x200>;
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
> + <&dma0 AT91_XDMAC_DT_PERID(8)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + clock-names = "spi_clk";
> + atmel,fifo-size = <32>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> dma0: dma-controller@e0068000 {
> @@ -233,6 +293,21 @@ usart4: serial@200 {
> atmel,fifo-size = <32>;
> status = "disabled";
> };
> +
> + spi4: spi@400 {
> + compatible = "atmel,at91rm9200-spi";
> + reg = <0x400 0x200>;
> + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
> + <&dma0 AT91_XDMAC_DT_PERID(10)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + clock-names = "spi_clk";
> + atmel,fifo-size = <32>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> timer0: timer@e008c000 {
> --
> 2.30.2
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 6/7] ARM: dts: lan966x: add flexcom I2C nodes
2022-03-04 15:35 [PATCH v2 0/7] ARM: dts: lan966x: dtsi improvements and KSwitch D10 support Michael Walle
` (4 preceding siblings ...)
2022-03-04 15:35 ` [PATCH v2 5/7] ARM: dts: lan966x: add flexcom SPI nodes Michael Walle
@ 2022-03-04 15:35 ` Michael Walle
2022-03-30 13:26 ` Claudiu.Beznea
2022-03-04 15:35 ` [PATCH v2 7/7] ARM: dts: lan966x: add basic Kontron KSwitch D10 support Michael Walle
6 siblings, 1 reply; 13+ messages in thread
From: Michael Walle @ 2022-03-04 15:35 UTC (permalink / raw)
To: Kavyasree Kotagiri, Nicolas Ferre
Cc: Arnd Bergmann, Olof Johansson, soc, linux-arm-kernel, devicetree,
linux-kernel, Rob Herring, Krzysztof Kozlowski,
Alexandre Belloni, Claudiu Beznea, Michael Walle
Add all I2C nodes of the flexcom IP blocks. The driver supports
FIFO, DMA or both combined. But the latter isn't working correctly.
Thus, skip the fifo-size property for now. DMA is doing single byte
reads in this case.
Keep the nodes disabled by default.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/boot/dts/lan966x.dtsi | 65 ++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index a61d394ad04d..95d58bdca3f0 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -120,6 +120,19 @@ spi0: spi@400 {
#size-cells = <0>;
status = "disabled";
};
+
+ i2c0: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
+ <&dma0 AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
flx1: flexcom@e0044000 {
@@ -158,6 +171,19 @@ spi1: spi@400 {
#size-cells = <0>;
status = "disabled";
};
+
+ i2c1: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
+ <&dma0 AT91_XDMAC_DT_PERID(4)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
trng: rng@e0048000 {
@@ -213,6 +239,19 @@ spi2: spi@400 {
#size-cells = <0>;
status = "disabled";
};
+
+ i2c2: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
+ <&dma0 AT91_XDMAC_DT_PERID(6)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
flx3: flexcom@e0064000 {
@@ -251,6 +290,19 @@ spi3: spi@400 {
#size-cells = <0>;
status = "disabled";
};
+
+ i2c3: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
+ <&dma0 AT91_XDMAC_DT_PERID(8)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
dma0: dma-controller@e0068000 {
@@ -308,6 +360,19 @@ spi4: spi@400 {
#size-cells = <0>;
status = "disabled";
};
+
+ i2c4: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
+ <&dma0 AT91_XDMAC_DT_PERID(10)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
timer0: timer@e008c000 {
--
2.30.2
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v2 6/7] ARM: dts: lan966x: add flexcom I2C nodes
2022-03-04 15:35 ` [PATCH v2 6/7] ARM: dts: lan966x: add flexcom I2C nodes Michael Walle
@ 2022-03-30 13:26 ` Claudiu.Beznea
0 siblings, 0 replies; 13+ messages in thread
From: Claudiu.Beznea @ 2022-03-30 13:26 UTC (permalink / raw)
To: michael, Kavyasree.Kotagiri, Nicolas.Ferre
Cc: arnd, olof, soc, linux-arm-kernel, devicetree, linux-kernel,
robh+dt, krzysztof.kozlowski, alexandre.belloni
On 04.03.2022 17:35, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add all I2C nodes of the flexcom IP blocks. The driver supports
> FIFO, DMA or both combined. But the latter isn't working correctly.
> Thus, skip the fifo-size property for now. DMA is doing single byte
> reads in this case.
>
> Keep the nodes disabled by default.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
> arch/arm/boot/dts/lan966x.dtsi | 65 ++++++++++++++++++++++++++++++++++
> 1 file changed, 65 insertions(+)
>
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index a61d394ad04d..95d58bdca3f0 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -120,6 +120,19 @@ spi0: spi@400 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + i2c0: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
> + <&dma0 AT91_XDMAC_DT_PERID(2)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> flx1: flexcom@e0044000 {
> @@ -158,6 +171,19 @@ spi1: spi@400 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + i2c1: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
> + <&dma0 AT91_XDMAC_DT_PERID(4)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> trng: rng@e0048000 {
> @@ -213,6 +239,19 @@ spi2: spi@400 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + i2c2: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
> + <&dma0 AT91_XDMAC_DT_PERID(6)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> flx3: flexcom@e0064000 {
> @@ -251,6 +290,19 @@ spi3: spi@400 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + i2c3: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
> + <&dma0 AT91_XDMAC_DT_PERID(8)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> dma0: dma-controller@e0068000 {
> @@ -308,6 +360,19 @@ spi4: spi@400 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + i2c4: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
> + <&dma0 AT91_XDMAC_DT_PERID(10)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> timer0: timer@e008c000 {
> --
> 2.30.2
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 7/7] ARM: dts: lan966x: add basic Kontron KSwitch D10 support
2022-03-04 15:35 [PATCH v2 0/7] ARM: dts: lan966x: dtsi improvements and KSwitch D10 support Michael Walle
` (5 preceding siblings ...)
2022-03-04 15:35 ` [PATCH v2 6/7] ARM: dts: lan966x: add flexcom I2C nodes Michael Walle
@ 2022-03-04 15:35 ` Michael Walle
6 siblings, 0 replies; 13+ messages in thread
From: Michael Walle @ 2022-03-04 15:35 UTC (permalink / raw)
To: Kavyasree Kotagiri, Nicolas Ferre
Cc: Arnd Bergmann, Olof Johansson, soc, linux-arm-kernel, devicetree,
linux-kernel, Rob Herring, Krzysztof Kozlowski,
Alexandre Belloni, Claudiu Beznea, Michael Walle
Add basic support for the Kontron KSwitch D10 MMT 6G-2GS which
features 6 Gigabit copper ports and two SFP cages. For now the
following is working:
- Kernel console
- SFP cages I2C bus and mux
- SPI
- SGPIO
- Watchdog
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/boot/dts/Makefile | 3 +-
...lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts | 159 ++++++++++++++++++
2 files changed, 161 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 085c43649d44..86dd0f9804ee 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -739,7 +739,8 @@ dtb-$(CONFIG_SOC_IMX7ULP) += \
imx7ulp-com.dtb \
imx7ulp-evk.dtb
dtb-$(CONFIG_SOC_LAN966) += \
- lan966x-pcb8291.dtb
+ lan966x-pcb8291.dtb \
+ lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-moxa-uc-8410a.dtb \
ls1021a-qds.dtb \
diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
new file mode 100644
index 000000000000..958678dec7ad
--- /dev/null
+++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for the Kontron KSwitch D10 MMT 6G-2GS
+ */
+
+/dts-v1/;
+#include "lan966x.dtsi"
+
+/ {
+ model = "Kontron KSwitch D10 MMT 6G-2GS";
+ compatible = "kontron,kswitch-d10-mmt-6g-2gs", "kontron,s1921",
+ "microchip,lan9668", "microchip,lan966";
+
+ aliases {
+ serial0 = &usart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
+ priority = <200>;
+ };
+
+ i2cmux {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mux-gpios = <&sgpio_out 3 2 GPIO_ACTIVE_HIGH>,
+ <&sgpio_out 3 3 GPIO_ACTIVE_HIGH>;
+ i2c-parent = <&i2c4>;
+
+ i2c4_0: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4_1: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ sfp0: sfp0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c4_0>;
+ los-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2500>;
+ tx-disable-gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in 0 2 GPIO_ACTIVE_HIGH>;
+ rate-select0-gpios = <&sgpio_out 2 0 GPIO_ACTIVE_HIGH>;
+ rate-select1-gpios = <&sgpio_out 2 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp1: sfp1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c4_1>;
+ los-gpios = <&sgpio_in 1 2 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in 1 3 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2500>;
+ tx-disable-gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in 0 3 GPIO_ACTIVE_HIGH>;
+ rate-select0-gpios = <&sgpio_out 2 2 GPIO_ACTIVE_HIGH>;
+ rate-select1-gpios = <&sgpio_out 2 3 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&flx0 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "okay";
+};
+
+&flx3 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
+ status = "okay";
+};
+
+&flx4 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+};
+
+&gpio {
+ usart0_pins: usart0-pins {
+ /* RXD, TXD */
+ pins = "GPIO_25", "GPIO_26";
+ function = "fc0_b";
+ };
+
+ sgpio_a_pins: sgpio-a-pins {
+ /* SCK, D0, D1, LD */
+ pins = "GPIO_32", "GPIO_33", "GPIO_34";
+ function = "sgpio_a";
+ };
+
+ sgpio_b_pins: sgpio-b-pins {
+ /* SCK, D0, D1, LD */
+ pins = "GPIO_64";
+ function = "sgpio_b";
+ };
+
+ fc3_b_pins: fc3-b-spi-pins {
+ /* SCK, MISO, MOSI */
+ pins = "GPIO_51", "GPIO_52", "GPIO_53";
+ function = "fc3_b";
+ };
+
+ fc4_b_pins: fc4-b-i2c-pins {
+ /* RXD, TXD */
+ pins = "GPIO_57", "GPIO_58";
+ function = "fc4_b";
+ };
+};
+
+&i2c4 {
+ pinctrl-0 = <&fc4_b_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usart0 {
+ pinctrl-0 = <&usart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sgpio {
+ pinctrl-0 = <&sgpio_a_pins>, <&sgpio_b_pins>;
+ pinctrl-names = "default";
+ bus-frequency = <8000000>;
+ /* arbitrary range because all GPIOs are in software mode */
+ microchip,sgpio-port-ranges = <0 11>;
+ status = "okay";
+};
+
+&sgpio_in {
+ ngpios = <128>;
+};
+
+&sgpio_out {
+ ngpios = <128>;
+};
+
+&spi3 {
+ pinctrl-0 = <&fc3_b_pins>;
+ pinctrl-names = "default";
+ cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
--
2.30.2
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