From: Krzysztof Kozlowski <krzk@kernel.org>
To: Chris Packham <Chris.Packham@alliedtelesis.co.nz>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"robh+dt@kernel.org" <robh+dt@kernel.org>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: "complete" dt-bindings for new SoC
Date: Wed, 13 Aug 2025 07:48:55 +0200 [thread overview]
Message-ID: <4f0ec956-d796-4c62-995b-f8a879b444f0@kernel.org> (raw)
In-Reply-To: <82c09e95-9856-42ec-b7a5-858fd06b888a@alliedtelesis.co.nz>
On 13/08/2025 06:56, Chris Packham wrote:
> Hi Devicetree Enthusiasts,
>
> A few times now I've been told that things would have been easier had I
> submitted a complete binding in the first place. I find myself looking
> at another new SoC (a Realtek Switch with and integrated ARM64 core this
> time). I'm also waiting on hardware so I figured I could probably get
> the ball rolling on a devicetree and I wanted to do a better job of
> writing the binding.
>
> Which brings be to the question. What does a "complete" binding mean to
> the devicetree maintainers? Are we talking about an overall binding for
> the chip that calls out peripherals (some which already exist) with a
> ref: ? Or a full binding in one document that covers everything in the
> chip? Does it need to be accompanied by an actual dts(i) for the chip?
Writing bindings doc describes that. I would add on top - if SoC has
multiple devices of same class, like multiple clock controllers or
resets, this should be taken into account if not sending all of them.
And by taking account I mean think how complete picture will look like.
One SoC for RISV-V is example of that...
Best regards,
Krzysztof
prev parent reply other threads:[~2025-08-13 5:48 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-13 4:56 Chris Packham
2025-08-13 5:48 ` Krzysztof Kozlowski [this message]
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