"complete" dt-bindings for new SoC

"complete" dt-bindings for new SoC

[Chris Packham]

Hi Devicetree Enthusiasts,

A few times now I've been told that things would have been easier had I 
submitted a complete binding in the first place. I find myself looking 
at another new SoC (a Realtek Switch with and integrated ARM64 core this 
time). I'm also waiting on hardware so I figured I could probably get 
the ball rolling on a devicetree and I wanted to do a better job of 
writing the binding.

Which brings be to the question. What does a "complete" binding mean to 
the devicetree maintainers? Are we talking about an overall binding for 
the chip that calls out peripherals (some which already exist) with a 
ref: ? Or a full binding in one document that covers everything in the 
chip? Does it need to be accompanied by an actual dts(i) for the chip?

Thanks,
Chris

Re: "complete" dt-bindings for new SoC

[Krzysztof Kozlowski]

On 13/08/2025 06:56, Chris Packham wrote:
> Hi Devicetree Enthusiasts,
> 
> A few times now I've been told that things would have been easier had I 
> submitted a complete binding in the first place. I find myself looking 
> at another new SoC (a Realtek Switch with and integrated ARM64 core this 
> time). I'm also waiting on hardware so I figured I could probably get 
> the ball rolling on a devicetree and I wanted to do a better job of 
> writing the binding.
> 
> Which brings be to the question. What does a "complete" binding mean to 
> the devicetree maintainers? Are we talking about an overall binding for 
> the chip that calls out peripherals (some which already exist) with a 
> ref: ? Or a full binding in one document that covers everything in the 
> chip? Does it need to be accompanied by an actual dts(i) for the chip?


Writing bindings doc describes that. I would add on top - if SoC has
multiple devices of same class, like multiple clock controllers or
resets, this should be taken into account if not sending all of them.
And by taking account I mean think how complete picture will look like.
One SoC for RISV-V is example of that...

Best regards,
Krzysztof