* [PATCH] phy: ti: gmii-sel: Enable USXGMII mode for J7200
@ 2024-10-10 14:48 Siddharth Vadapalli
2024-10-10 20:01 ` Roger Quadros
2024-10-12 17:50 ` Vinod Koul
0 siblings, 2 replies; 3+ messages in thread
From: Siddharth Vadapalli @ 2024-10-10 14:48 UTC (permalink / raw)
To: vkoul, kishon, thomas.richard, krzysztof.kozlowski, rogerq,
florian.fainelli, c-vankar, afd
Cc: linux-phy, linux-kernel, linux-arm-kernel, srk, s-vadapalli
TI's J7200 SoC supports USXGMII mode with the CPSW5G instance's MAC Port1.
Add USXGMII mode to the extra_modes member of J7200's SoC data.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Hello,
This patch is based on linux-next tagged next-20241010.
Regards,
Siddharth.
drivers/phy/ti/phy-gmii-sel.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index 103b266fec77..e0ca59ae3153 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -230,7 +230,8 @@ static const
struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
.use_of_data = true,
.regfields = phy_gmii_sel_fields_am654,
- .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
+ .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) |
+ BIT(PHY_INTERFACE_MODE_USXGMII),
.num_ports = 4,
.num_qsgmii_main_ports = 1,
};
--
2.40.1
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] phy: ti: gmii-sel: Enable USXGMII mode for J7200
2024-10-10 14:48 [PATCH] phy: ti: gmii-sel: Enable USXGMII mode for J7200 Siddharth Vadapalli
@ 2024-10-10 20:01 ` Roger Quadros
2024-10-12 17:50 ` Vinod Koul
1 sibling, 0 replies; 3+ messages in thread
From: Roger Quadros @ 2024-10-10 20:01 UTC (permalink / raw)
To: Siddharth Vadapalli, vkoul, kishon, thomas.richard,
krzysztof.kozlowski, florian.fainelli, c-vankar, afd
Cc: linux-phy, linux-kernel, linux-arm-kernel, srk
On 10/10/2024 17:48, Siddharth Vadapalli wrote:
> TI's J7200 SoC supports USXGMII mode with the CPSW5G instance's MAC Port1.
> Add USXGMII mode to the extra_modes member of J7200's SoC data.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] phy: ti: gmii-sel: Enable USXGMII mode for J7200
2024-10-10 14:48 [PATCH] phy: ti: gmii-sel: Enable USXGMII mode for J7200 Siddharth Vadapalli
2024-10-10 20:01 ` Roger Quadros
@ 2024-10-12 17:50 ` Vinod Koul
1 sibling, 0 replies; 3+ messages in thread
From: Vinod Koul @ 2024-10-12 17:50 UTC (permalink / raw)
To: kishon, thomas.richard, krzysztof.kozlowski, rogerq,
florian.fainelli, c-vankar, afd, Siddharth Vadapalli
Cc: linux-phy, linux-kernel, linux-arm-kernel, srk
On Thu, 10 Oct 2024 20:18:45 +0530, Siddharth Vadapalli wrote:
> TI's J7200 SoC supports USXGMII mode with the CPSW5G instance's MAC Port1.
> Add USXGMII mode to the extra_modes member of J7200's SoC data.
>
>
Applied, thanks!
[1/1] phy: ti: gmii-sel: Enable USXGMII mode for J7200
commit: 9e544d46a2d11a0cb8b30d8ad4409c59bc168ce2
Best regards,
--
~Vinod
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-10-10 14:48 [PATCH] phy: ti: gmii-sel: Enable USXGMII mode for J7200 Siddharth Vadapalli
2024-10-10 20:01 ` Roger Quadros
2024-10-12 17:50 ` Vinod Koul
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