Re: [PATCH v2 2/4] pinctrl: samsung: add dedicated SoC eint suspend/resume callbacks

["André Draszik" <andre.draszik@linaro.org>]

On Thu, 2025-03-06 at 11:57 +0000, André Draszik wrote:
> On Sat, 2025-03-01 at 11:43 +0000, Peter Griffin wrote:
> > [...]
> >  
> > -static void exynos_pinctrl_resume_bank(
> > -				struct samsung_pinctrl_drv_data *drvdata,
> > -				struct samsung_pin_bank *bank)
> > +void exynos_pinctrl_resume(struct samsung_pin_bank *bank)
> >  {
> >  	struct exynos_eint_gpio_save *save = bank->soc_priv;
> >  	void __iomem *regs = bank->eint_base;
> >  
> > -	if (clk_enable(bank->drvdata->pclk)) {
> > -		dev_err(bank->gpio_chip.parent,
> > -			"unable to enable clock for restoring state\n");
> > -		return;
> > +	if (bank->eint_type == EINT_TYPE_GPIO) {
> > +		pr_debug("%s:     con %#010x => %#010x\n", bank->name,
> > +			 readl(regs + EXYNOS_GPIO_ECON_OFFSET
> > +			       + bank->eint_offset), save->eint_con);
> > +		pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
> > +			 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
> > +			       + 2 * bank->eint_offset), save->eint_fltcon0);
> > +		pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
> > +			 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
> > +			       + 2 * bank->eint_offset + 4),
> > +			       save->eint_fltcon1);

The indent on this last line is a bit off.

> > +		pr_debug("%s:    mask %#010x => %#010x\n", bank->name,
> > +			 readl(regs + bank->irq_chip->eint_mask
> > +			       + bank->eint_offset), save->eint_mask);
> > +
> > +		writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
> > +		       + bank->eint_offset);
> > +		writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
> > +		       + 2 * bank->eint_offset);
> > +		writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
> > +		       + 2 * bank->eint_offset + 4);
> > +		writel(save->eint_mask, regs + bank->irq_chip->eint_mask
> > +		       + bank->eint_offset);
> >  	}
> > -
> > -	pr_debug("%s:     con %#010x => %#010x\n", bank->name,
> > -			readl(regs + EXYNOS_GPIO_ECON_OFFSET
> > -			+ bank->eint_offset), save->eint_con);
> > -	pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
> > -			readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
> > -			+ 2 * bank->eint_offset), save->eint_fltcon0);
> > -	pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
> > -			readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
> > -			+ 2 * bank->eint_offset + 4), save->eint_fltcon1);
> > -	pr_debug("%s:    mask %#010x => %#010x\n", bank->name,
> > -			readl(regs + bank->irq_chip->eint_mask
> > -			+ bank->eint_offset), save->eint_mask);
> > -
> > -	writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
> > -						+ bank->eint_offset);
> > -	writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
> > -						+ 2 * bank->eint_offset);
> > -	writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
> > -						+ 2 * bank->eint_offset + 4);
> > -	writel(save->eint_mask, regs + bank->irq_chip->eint_mask
> > -						+ bank->eint_offset);
> > -
> > -	clk_disable(bank->drvdata->pclk);
> >  }
> >  
> > -static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvdata,
> > -					   struct samsung_pin_bank *bank)
> > +void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank)
> >  {
> >  	struct exynos_eint_gpio_save *save = bank->soc_priv;
> >  	void __iomem *regs = bank->eint_base;
> >  
> > -	if (clk_enable(bank->drvdata->pclk)) {
> > -		dev_err(bank->gpio_chip.parent,
> > -			"unable to enable clock for restoring state\n");
> > -		return;
> > +	if (bank->eint_type == EINT_TYPE_GPIO) {
> > +		/* exynosautov920 has eint_con_offset for all but one bank */
> > +		if (!bank->eint_con_offset)
> > +			exynos_pinctrl_resume(bank);
> > +
> > +		pr_debug("%s:     con %#010x => %#010x\n", bank->name,
> > +			 readl(regs + bank->pctl_offset + bank->eint_con_offset),
> > +			       save->eint_con);

and here

Cheers,
Andre'