From: Paolo Bonzini <pbonzini@redhat.com>
To: Anup Patel <anup.patel@wdc.com>, Shuah Khan <shuah@kernel.org>,
Atish Patra <atishp@atishpatra.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alistair Francis <Alistair.Francis@wdc.com>,
Anup Patel <anup@brainfault.org>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH 2/4] RISC-V: KVM: Add VM capability to allow userspace get GPA size
Date: Fri, 26 Nov 2021 17:13:36 +0100 [thread overview]
Message-ID: <4fcb162a-738b-64e7-6326-9f9967d1b8a8@redhat.com> (raw)
In-Reply-To: <20211126154020.342924-3-anup.patel@wdc.com>
On 11/26/21 16:40, Anup Patel wrote:
> The GPA size supported for a RISC-V Guest/VM is based on the MMU mode
> used by G-stage translation. The KVM RISC-V will detect and use the
> best possible MMU mode for the G-stage in kvm_arch_init().
>
> We add a RISC-V specific VM capability KVM_CAP_RISCV_VM_GPA_SIZE which
You can make it just KVM_CAP_VM_GPA_BITS instead - it's useful on other
architectures as well.
Paolo
> can be used by KVM userspace to get guest physical address (GPA) size
> (i.e. number of GPA bits) supported for a Guest/VM.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> arch/riscv/include/asm/kvm_host.h | 1 +
> arch/riscv/kvm/mmu.c | 5 +++++
> arch/riscv/kvm/vm.c | 3 +++
> include/uapi/linux/kvm.h | 1 +
> 4 files changed, 10 insertions(+)
>
> diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> index 37589b953bcb..ae5d238607fe 100644
> --- a/arch/riscv/include/asm/kvm_host.h
> +++ b/arch/riscv/include/asm/kvm_host.h
> @@ -221,6 +221,7 @@ void kvm_riscv_stage2_free_pgd(struct kvm *kvm);
> void kvm_riscv_stage2_update_hgatp(struct kvm_vcpu *vcpu);
> void kvm_riscv_stage2_mode_detect(void);
> unsigned long kvm_riscv_stage2_mode(void);
> +int kvm_riscv_stage2_gpa_size(void);
>
> void kvm_riscv_stage2_vmid_detect(void);
> unsigned long kvm_riscv_stage2_vmid_bits(void);
> diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
> index 9ffd0255af43..9b6d6465094f 100644
> --- a/arch/riscv/kvm/mmu.c
> +++ b/arch/riscv/kvm/mmu.c
> @@ -760,3 +760,8 @@ unsigned long kvm_riscv_stage2_mode(void)
> {
> return stage2_mode >> HGATP_MODE_SHIFT;
> }
> +
> +int kvm_riscv_stage2_gpa_size(void)
> +{
> + return stage2_gpa_bits;
> +}
> diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c
> index fb18af34a4b5..ae97f6929897 100644
> --- a/arch/riscv/kvm/vm.c
> +++ b/arch/riscv/kvm/vm.c
> @@ -82,6 +82,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
> case KVM_CAP_NR_MEMSLOTS:
> r = KVM_USER_MEM_SLOTS;
> break;
> + case KVM_CAP_RISCV_VM_GPA_SIZE:
> + r = kvm_riscv_stage2_gpa_size();
> + break;
> default:
> r = 0;
> break;
> diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
> index 1daa45268de2..dac98df3101d 100644
> --- a/include/uapi/linux/kvm.h
> +++ b/include/uapi/linux/kvm.h
> @@ -1131,6 +1131,7 @@ struct kvm_ppc_resize_hpt {
> #define KVM_CAP_EXIT_ON_EMULATION_FAILURE 204
> #define KVM_CAP_ARM_MTE 205
> #define KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM 206
> +#define KVM_CAP_RISCV_VM_GPA_SIZE 207
>
> #ifdef KVM_CAP_IRQ_ROUTING
>
>
next prev parent reply other threads:[~2021-11-26 16:15 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-26 15:40 [PATCH 0/4] KVM RISC-V 64-bit selftests support Anup Patel
2021-11-26 15:40 ` [PATCH 1/4] RISC-V: KVM: Forward SBI experimental and vendor extensions Anup Patel
2021-11-26 16:12 ` Paolo Bonzini
2021-11-29 3:39 ` Anup Patel
2021-11-26 15:40 ` [PATCH 2/4] RISC-V: KVM: Add VM capability to allow userspace get GPA size Anup Patel
2021-11-26 16:13 ` Paolo Bonzini [this message]
2021-11-29 3:40 ` Anup Patel
2021-11-26 15:40 ` [PATCH 3/4] KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile Anup Patel
2021-11-26 16:15 ` Paolo Bonzini
2021-11-29 3:43 ` Anup Patel
2021-11-26 15:40 ` [PATCH 4/4] KVM: selftests: Add initial support for RISC-V 64-bit Anup Patel
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