* [PATCH] mtd: spi-nor: enable 4B opcodes for n25q256a
@ 2019-05-03 8:53 Simon Goldschmidt
2019-05-03 10:00 ` Marek Vasut
0 siblings, 1 reply; 4+ messages in thread
From: Simon Goldschmidt @ 2019-05-03 8:53 UTC (permalink / raw)
To: Marek Vasut, linux-mtd
Cc: Simon Goldschmidt, linux-kernel, Brian Norris,
Richard Weinberger, David Woodhouse, Boris Brezillon,
Tudor Ambarus
Tested on socfpga cyclone5 where this is required to ensure that the
boot rom can access this flash after warm reboot.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---
drivers/mtd/spi-nor/spi-nor.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index fae147452..4cdec2cc2 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1874,7 +1874,7 @@ static const struct flash_info spi_nor_ids[] = {
{ "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
- { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
--
2.20.1
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] mtd: spi-nor: enable 4B opcodes for n25q256a
2019-05-03 8:53 [PATCH] mtd: spi-nor: enable 4B opcodes for n25q256a Simon Goldschmidt
@ 2019-05-03 10:00 ` Marek Vasut
2019-05-03 10:37 ` Simon Goldschmidt
0 siblings, 1 reply; 4+ messages in thread
From: Marek Vasut @ 2019-05-03 10:00 UTC (permalink / raw)
To: Simon Goldschmidt, linux-mtd
Cc: linux-kernel, Brian Norris, Richard Weinberger, David Woodhouse,
Boris Brezillon, Tudor Ambarus
On 5/3/19 10:53 AM, Simon Goldschmidt wrote:
> Tested on socfpga cyclone5 where this is required to ensure that the
> boot rom can access this flash after warm reboot.
Are you sure _all_ variants of the N25Q256 support 4NB opcodes ?
I think there were some which didn't, but I might be wrong.
> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> ---
>
> drivers/mtd/spi-nor/spi-nor.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index fae147452..4cdec2cc2 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -1874,7 +1874,7 @@ static const struct flash_info spi_nor_ids[] = {
> { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
> { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
> { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
> - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> + { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
> { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
> { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] mtd: spi-nor: enable 4B opcodes for n25q256a
2019-05-03 10:00 ` Marek Vasut
@ 2019-05-03 10:37 ` Simon Goldschmidt
2019-05-03 11:27 ` Marek Vasut
0 siblings, 1 reply; 4+ messages in thread
From: Simon Goldschmidt @ 2019-05-03 10:37 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-mtd, linux-kernel, Brian Norris, Richard Weinberger,
David Woodhouse, Boris Brezillon, Tudor Ambarus
On Fri, May 3, 2019 at 12:00 PM Marek Vasut <marek.vasut@gmail.com> wrote:
>
> On 5/3/19 10:53 AM, Simon Goldschmidt wrote:
> > Tested on socfpga cyclone5 where this is required to ensure that the
> > boot rom can access this flash after warm reboot.
>
> Are you sure _all_ variants of the N25Q256 support 4NB opcodes ?
> I think there were some which didn't, but I might be wrong.
Oh, damn, you're right. The documentation [1] statest that 4-byte erase and
program opcodes are only supported for part numbers N25Q256A83ESF40x,
N25Q256A83E1240x and N25QA83ESFA0F.
Any idea of how I can still enable 4-byte opcodes for my chip?
Regards,
Simon
>
> > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> > ---
> >
> > drivers/mtd/spi-nor/spi-nor.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> > index fae147452..4cdec2cc2 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -1874,7 +1874,7 @@ static const struct flash_info spi_nor_ids[] = {
> > { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
> > { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
> > { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
> > - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > + { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> > { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
> > { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
> > { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
> >
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] mtd: spi-nor: enable 4B opcodes for n25q256a
2019-05-03 10:37 ` Simon Goldschmidt
@ 2019-05-03 11:27 ` Marek Vasut
0 siblings, 0 replies; 4+ messages in thread
From: Marek Vasut @ 2019-05-03 11:27 UTC (permalink / raw)
To: Simon Goldschmidt
Cc: linux-mtd, linux-kernel, Brian Norris, Richard Weinberger,
David Woodhouse, Boris Brezillon, Tudor Ambarus
On 5/3/19 12:37 PM, Simon Goldschmidt wrote:
> On Fri, May 3, 2019 at 12:00 PM Marek Vasut <marek.vasut@gmail.com> wrote:
>>
>> On 5/3/19 10:53 AM, Simon Goldschmidt wrote:
>>> Tested on socfpga cyclone5 where this is required to ensure that the
>>> boot rom can access this flash after warm reboot.
>>
>> Are you sure _all_ variants of the N25Q256 support 4NB opcodes ?
>> I think there were some which didn't, but I might be wrong.
>
> Oh, damn, you're right. The documentation [1] statest that 4-byte erase and
> program opcodes are only supported for part numbers N25Q256A83ESF40x,
> N25Q256A83E1240x and N25QA83ESFA0F.
;-)
> Any idea of how I can still enable 4-byte opcodes for my chip?
Maybe SFDP tables contains some information whether the chip supports
the 4B opcodes ?
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 4+ messages in thread
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2019-05-03 8:53 [PATCH] mtd: spi-nor: enable 4B opcodes for n25q256a Simon Goldschmidt
2019-05-03 10:00 ` Marek Vasut
2019-05-03 10:37 ` Simon Goldschmidt
2019-05-03 11:27 ` Marek Vasut
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