From: Yicong Yang <yangyicong@huawei.com>
To: Will Deacon <will@kernel.org>
Cc: <yangyicong@hisilicon.com>, <mark.rutland@arm.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <hejunhao3@huawei.com>,
<jonathan.cameron@huawei.com>, <prime.zeng@hisilicon.com>,
<linuxarm@huawei.com>, <wangyushan12@huawei.com>
Subject: Re: [RESEND PATCH v3 7/8] drivers/perf: hisi: Add support for HiSilicon NoC PMU
Date: Tue, 15 Jul 2025 16:09:34 +0800 [thread overview]
Message-ID: <501e61fb-2dc5-c207-4bfd-1d3f23cd2c28@huawei.com> (raw)
In-Reply-To: <aHUeJ1ovziG1rTyW@willie-the-truck>
On 2025/7/14 23:11, Will Deacon wrote:
> On Thu, Jun 19, 2025 at 08:55:56PM +0800, Yicong Yang wrote:
>> From: Yicong Yang <yangyicong@hisilicon.com>
>>
>> Adds the support for HiSilicon NoC (Network on Chip) PMU which
>> will be used to monitor the events on the system bus. The PMU
>> device will be named after the SCL ID (either Super CPU cluster
>> or Super IO cluster) and the index ID, just similar to other
>> HiSilicon Uncore PMUs. Below PMU formats are provided besides
>> the event:
>>
>> - ch: the transaction channel (data, request, response, etc) which
>> can be used to filter the counting.
>> - tt_en: tracetag filtering enable. Just as other HiSilicon Uncore
>> PMUs the NoC PMU supports only counting the transactions with
>> tracetag.
>>
>> The NoC PMU doesn't have an interrupt to indicate the overflow.
>> However we have a 64 bit counter which is large enough and it's
>> nearly impossible to overflow.
>>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
>> ---
>> Documentation/admin-guide/perf/hisi-pmu.rst | 11 +
>> drivers/perf/hisilicon/Makefile | 3 +-
>> drivers/perf/hisilicon/hisi_uncore_noc_pmu.c | 392 +++++++++++++++++++
>> 3 files changed, 405 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/perf/hisilicon/hisi_uncore_noc_pmu.c
>
> [...]
>
>> +static int hisi_noc_pmu_dev_init(struct platform_device *pdev, struct hisi_pmu *noc_pmu)
>> +{
>> + hisi_uncore_pmu_init_topology(noc_pmu, &pdev->dev);
>> +
>> + if (noc_pmu->topo.scl_id < 0)
>> + return dev_err_probe(&pdev->dev, -EINVAL, "failed to get scl-id\n");
>> +
>> + if (noc_pmu->topo.index_id < 0)
>> + return dev_err_probe(&pdev->dev, -EINVAL, "failed to get idx-id\n");
>> +
>> + if (noc_pmu->topo.sub_id < 0)
>> + return dev_err_probe(&pdev->dev, -EINVAL, "failed to get sub-id\n");
>> +
>> + noc_pmu->base = devm_platform_ioremap_resource(pdev, 0);
>> + if (IS_ERR(noc_pmu->base))
>> + return dev_err_probe(&pdev->dev, PTR_ERR(noc_pmu->base),
>> + "fail to remap io memory\n");
>> +
>> + noc_pmu->on_cpu = -1;
>> + noc_pmu->dev = &pdev->dev;
>> + noc_pmu->ops = &hisi_uncore_noc_ops;
>> + noc_pmu->pmu_events.attr_groups = hisi_noc_pmu_attr_groups;
>> + noc_pmu->num_counters = NOC_PMU_NR_COUNTERS;
>> + noc_pmu->counter_bits = NOC_PMU_COUNTER_BITS;
>> + noc_pmu->check_event = NOC_PMU_EVENT_CTRL_TYPE;
>> + noc_pmu->identifier = readl(noc_pmu->base + NOC_PMU_VERSION);
>
> Would it be worth going straight to an ACPI-based lookup for this lot?
> The earlier patches in the series rework the existing drivers to go in
> that direction as it's easier to extend, so it seems a little odd for
> new driver code to revert back to e.g. reeading the version number.
>
> Same for the misc node driver in the next patch.
>
ok. was planned to change to that when new version comes with new capabilities and
hardware interface, but it's easy to change to that. will update.
Thanks.
next prev parent reply other threads:[~2025-07-15 8:09 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-19 12:55 [RESEND PATCH v3 0/8] General updates and two new drivers for HiSilicon Uncore PMU Yicong Yang
2025-06-19 12:55 ` [RESEND PATCH v3 1/8] drivers/perf: hisi: Simplify the probe process for each DDRC version Yicong Yang
2025-06-19 12:55 ` [RESEND PATCH v3 2/8] drivers/perf: hisi: Add support for HiSilicon DDRC v3 PMU driver Yicong Yang
2025-06-19 12:55 ` [RESEND PATCH v3 3/8] drivers/perf: hisi: Use ACPI driver_data to retrieve SLLC PMU information Yicong Yang
2025-06-19 12:55 ` [RESEND PATCH v3 4/8] drivers/perf: hisi: Add support for HiSilicon SLLC v3 PMU driver Yicong Yang
2025-06-19 12:55 ` [RESEND PATCH v3 5/8] drivers/perf: hisi: Relax the event number check of v2 PMUs Yicong Yang
2025-06-19 12:55 ` [RESEND PATCH v3 6/8] drivers/perf: hisi: Support PMUs with no interrupt Yicong Yang
2025-06-19 12:55 ` [RESEND PATCH v3 7/8] drivers/perf: hisi: Add support for HiSilicon NoC PMU Yicong Yang
2025-07-14 15:11 ` Will Deacon
2025-07-15 8:09 ` Yicong Yang [this message]
2025-06-19 12:55 ` [RESEND PATCH v3 8/8] drivers/perf: hisi: Add support for HiSilicon MN PMU driver Yicong Yang
2025-07-01 12:36 ` [RESEND PATCH v3 0/8] General updates and two new drivers for HiSilicon Uncore PMU Yicong Yang
2025-07-13 16:27 ` Jonathan Cameron
2025-07-13 20:02 ` Will Deacon
2025-07-14 15:10 ` Will Deacon
-- strict thread matches above, loose matches on Subject: below --
2025-04-25 9:00 Yicong Yang
2025-04-25 9:00 ` [RESEND PATCH v3 7/8] drivers/perf: hisi: Add support for HiSilicon NoC PMU Yicong Yang
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