From: "Yiru Zhang (张熠儒)" <Yiru.Zhang@mediatek.com>
To: "james.clark@linaro.org" <james.clark@linaro.org>,
"mike.leach@linaro.org" <mike.leach@linaro.org>,
"alexander.shishkin@linux.intel.com"
<alexander.shishkin@linux.intel.com>,
"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
"suzuki.poulose@arm.com" <suzuki.poulose@arm.com>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-mediatek@lists.infradead.org"
<linux-mediatek@lists.infradead.org>,
"coresight@lists.linaro.org" <coresight@lists.linaro.org>
Subject: Re: [PATCH] [Patch v1]Add ETE devarch condition in etm4_init_iomem_access
Date: Wed, 9 Apr 2025 03:10:50 +0000 [thread overview]
Message-ID: <5099052b6ba2bdd431c06349d81ef3acfb4d9b5d.camel@mediatek.com> (raw)
In-Reply-To: <98f6fa74-f14e-48f1-b550-c1ff962df53d@arm.com>
hi Suzuki, thanks for your reply.
If no ETE condition in etm4_init_iomem_access, the function will return
false and influence following process.
I will send v2 patch using a switch case.
Thanks,
Yiru
On Tue, 2025-04-08 at 10:05 +0100, Suzuki K Poulose wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>
>
> Hi Yiru
>
>
>
> On 08/04/2025 08:36, yiru zhang wrote:
> > Due to ETE supported, so add ETE devarch condition in
> > etm4_init_iomem_access.
>
> Is there a reason why you cannot use the "system instructions to
> access
> the ETE" ?
>
> The patch as such is fine by me (withe some minor styling nits). But,
> we
> do not recommend using the MMIO for ETE, when it can be accessed
> directly by sysreg.
>
> FWIW, if you remove the "mmio base" address from the DT/ACPI, it
> should automatically use the system instructions for ETE.
>
>
>
>
> > Signed-off-by: yiru zhang <yiru.zhang@mediatek.com>
> > ---
> > drivers/hwtracing/coresight/coresight-etm4x-core.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > index 2b8f10463840..971b9f0fe5e4 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > @@ -1135,8 +1135,9 @@ static bool etm4_init_iomem_access(struct
> > etmv4_drvdata *drvdata,
> > * with MMIO. But we cannot touch the OSLK until we are
> > * sure this is an ETM. So rely only on the TRCDEVARCH.
> > */
> > - if ((devarch & ETM_DEVARCH_ID_MASK) !=
> > ETM_DEVARCH_ETMv4x_ARCH) {
> > - pr_warn_once("TRCDEVARCH doesn't match ETMv4
> > architecture\n");
> > + if ((devarch & ETM_DEVARCH_ID_MASK) !=
> > ETM_DEVARCH_ETMv4x_ARCH \
> > + && (devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETE_ARCH) {
>
> We could use a switch case ?
>
> switch (devarch & ETM_DEVARCH_ID_MASK) {
> case ETM_DEVARCH_ETMv4x_ARCH:
> case ETM_DEVARCH_ETE_ARCH:
> break;
> default:
> pr_warn_once("Unknown ETM architecture: %x\n",
> devarch & ETM_DEVARCH_ID_MASK);
> return false;
> }
>
> Suzuki
>
> > + pr_warn_once("TRCDEVARCH doesn't match ETMv4&ETE
> > architecture\n");
> > return false;
> > }
> >
>
>
prev parent reply other threads:[~2025-04-09 3:10 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-08 7:36 yiru zhang
2025-04-08 9:05 ` Suzuki K Poulose
2025-04-09 3:10 ` Yiru Zhang (张熠儒) [this message]
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