From: Yi Liu <yi.l.liu@intel.com>
To: Lu Baolu <baolu.lu@linux.intel.com>,
Joerg Roedel <joro@8bytes.org>, "Will Deacon" <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
"Jason Gunthorpe" <jgg@ziepe.ca>,
Kevin Tian <kevin.tian@intel.com>
Cc: <iommu@lists.linux.dev>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/1] iommu/vt-d: Move PCI PASID enablement to probe path
Date: Mon, 19 Aug 2024 11:14:24 +0800 [thread overview]
Message-ID: <511f140b-2792-47b0-b366-cbbad6e80239@intel.com> (raw)
In-Reply-To: <20240816104945.97160-1-baolu.lu@linux.intel.com>
On 2024/8/16 18:49, Lu Baolu wrote:
> Currently, PCI PASID is enabled alongside PCI ATS when an iommu domain is
> attached to the device and disabled when the device transitions to block
> translation mode. This approach is inappropriate as PCI PASID is a device
> feature independent of the type of the attached domain.
>
> Enable PCI PASID during the IOMMU device probe and disables it during the
> release path.
>
> Suggested-by: Yi Liu <yi.l.liu@intel.com>
> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
> ---
> drivers/iommu/intel/iommu.c | 27 +++++++++++++--------------
> 1 file changed, 13 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> index 9ff8b83c19a3..5a8080c71b04 100644
> --- a/drivers/iommu/intel/iommu.c
> +++ b/drivers/iommu/intel/iommu.c
> @@ -1322,15 +1322,6 @@ static void iommu_enable_pci_caps(struct device_domain_info *info)
> return;
>
> pdev = to_pci_dev(info->dev);
> -
> - /* The PCIe spec, in its wisdom, declares that the behaviour of
> - the device if you enable PASID support after ATS support is
> - undefined. So always enable PASID support on devices which
> - have it, even if we can't yet know if we're ever going to
> - use it. */
> - if (info->pasid_supported && !pci_enable_pasid(pdev, info->pasid_supported & ~1))
> - info->pasid_enabled = 1;
> -
> if (info->ats_supported && pci_ats_page_aligned(pdev) &&
> !pci_enable_ats(pdev, VTD_PAGE_SHIFT)) {
> info->ats_enabled = 1;
> @@ -1352,11 +1343,6 @@ static void iommu_disable_pci_caps(struct device_domain_info *info)
> info->ats_enabled = 0;
> domain_update_iotlb(info->domain);
> }
> -
> - if (info->pasid_enabled) {
> - pci_disable_pasid(pdev);
> - info->pasid_enabled = 0;
> - }
> }
>
> static void intel_flush_iotlb_all(struct iommu_domain *domain)
> @@ -4110,6 +4096,16 @@ static struct iommu_device *intel_iommu_probe_device(struct device *dev)
> }
> }
>
> + /*
> + * The PCIe spec, in its wisdom, declares that the behaviour of the
> + * device is undefined if you enable PASID support after ATS support.
> + * So always enable PASID support on devices which have it, even if
> + * we can't yet know if we're ever going to use it.
> + */
> + if (info->pasid_supported &&
> + !pci_enable_pasid(pdev, info->pasid_supported & ~1))
> + info->pasid_enabled = 1;
> +
> intel_iommu_debugfs_create_dev(info);
>
> return &iommu->iommu;
> @@ -4128,6 +4124,9 @@ static void intel_iommu_release_device(struct device *dev)
> struct device_domain_info *info = dev_iommu_priv_get(dev);
> struct intel_iommu *iommu = info->iommu;
>
> + if (info->pasid_enabled)
> + pci_disable_pasid(to_pci_dev(dev));
> +
would it make sense to move this behind the
intel_iommu_debugfs_remove_dev(info)? This seems to mirror the order of the
intel_iommu_probe_device(). Or you may set info->pasid_enabled to 0 in case
of any code uses it before info is freed if keeping this order. Otherwise,
lgtm. thanks for the quick action. :)
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
> mutex_lock(&iommu->iopf_lock);
> if (dev_is_pci(dev) && pci_ats_supported(to_pci_dev(dev)))
> device_rbtree_remove(info);
--
Regards,
Yi Liu
next prev parent reply other threads:[~2024-08-19 3:10 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-16 10:49 Lu Baolu
2024-08-16 12:16 ` Vasant Hegde
2024-08-16 13:09 ` Baolu Lu
2024-08-16 13:31 ` Jason Gunthorpe
2024-08-19 6:34 ` Vasant Hegde
2024-08-19 7:09 ` Baolu Lu
2024-08-19 7:11 ` Baolu Lu
2024-08-19 12:34 ` Jason Gunthorpe
2024-08-20 4:10 ` Baolu Lu
2024-08-20 8:30 ` Vasant Hegde
2024-08-20 8:55 ` Yi Liu
2024-08-20 13:52 ` Jason Gunthorpe
2024-08-20 13:51 ` Jason Gunthorpe
2024-08-26 9:11 ` Vasant Hegde
2024-08-19 7:32 ` Yi Liu
2024-08-19 3:14 ` Yi Liu [this message]
2024-08-19 3:34 ` Baolu Lu
2024-08-19 4:51 ` Yi Liu
2024-08-19 5:15 ` Baolu Lu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=511f140b-2792-47b0-b366-cbbad6e80239@intel.com \
--to=yi.l.liu@intel.com \
--cc=baolu.lu@linux.intel.com \
--cc=iommu@lists.linux.dev \
--cc=jgg@ziepe.ca \
--cc=joro@8bytes.org \
--cc=kevin.tian@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=robin.murphy@arm.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
Powered by JetHome