From: Jie Luo <jie.luo@oss.qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney@redhat.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com,
quic_leiwei@quicinc.com, quic_suruchia@quicinc.com
Subject: Re: [PATCH 09/12] clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocks
Date: Wed, 29 Jul 2026 21:18:05 +0800 [thread overview]
Message-ID: <5215ceda-0f13-44ce-93ef-41985979ce7f@oss.qualcomm.com> (raw)
In-Reply-To: <c08192fb-7d5a-43b5-93ce-f17c5a0b3cb1@oss.qualcomm.com>
On 7/28/2026 5:32 PM, Konrad Dybcio wrote:
> On 7/24/26 5:00 PM, Luo Jie wrote:
>> Some CMN PLL output clocks require a hardware gate in addition to a
>> fixed rate. The gate control bits reside in the register
>> CMN_PLL_OUTPUT_RELATED_1 (0x79c). Each such clock is registered as a
>> composite clock combining a clk_fixed_rate provider with a clk_gate.
>
> Would toggling this register in .enable/.disable not be good enough?
> Do we need to register a separate gate?
>
> Konrad
Yes. Toggling the bit directly in custom .enable/.disable is simpler and
more consistent with the rest of this driver (every other clock here
uses regmap). Will switch to a single clk_hw with hand-written
.enable/.disable/.is_enabled/.recalc_rate ops on
CMN_PLL_OUTPUT_RELATED_1.
next prev parent reply other threads:[~2026-07-29 13:18 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-24 15:00 [PATCH 00/12] clk: qcom: ipq-cmn-pll: Add IPQ5210 CMN PLL support Luo Jie
2026-07-24 15:00 ` [PATCH 01/12] clk: qcom: ipq-cmn-pll: Use devm_clk_hw_register_fixed_rate_parent_data Luo Jie
2026-07-24 15:50 ` Konrad Dybcio
2026-07-24 15:00 ` [PATCH 02/12] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5210 SoC Luo Jie
2026-07-24 15:00 ` [PATCH 03/12] clk: qcom: ipq-cmn-pll: Add analog soft-reset helper Luo Jie
2026-07-24 15:00 ` [PATCH 04/12] clk: qcom: ipq-cmn-pll: Add NSS clock support Luo Jie
2026-07-28 9:29 ` Konrad Dybcio
2026-07-29 13:15 ` Jie Luo
2026-07-24 15:00 ` [PATCH 05/12] clk: qcom: ipq-cmn-pll: Add PPE " Luo Jie
2026-07-24 15:00 ` [PATCH 06/12] clk: qcom: ipq-cmn-pll: Add PON reference " Luo Jie
2026-07-24 15:00 ` [PATCH 07/12] clk: qcom: ipq-cmn-pll: Add EPHY-RAW " Luo Jie
2026-07-24 15:00 ` [PATCH 08/12] clk: composite: Export devm_clk_hw_register_composite_pdata Luo Jie
2026-07-24 16:01 ` Brian Masney
2026-07-28 2:20 ` Jie Luo
2026-07-24 15:00 ` [PATCH 09/12] clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocks Luo Jie
2026-07-28 9:32 ` Konrad Dybcio
2026-07-29 13:18 ` Jie Luo [this message]
2026-07-24 15:00 ` [PATCH 10/12] clk: qcom: ipq-cmn-pll: Add all output clocks for IPQ5210 Luo Jie
2026-07-24 15:00 ` [PATCH 11/12] arm64: dts: qcom: ipq5210: Add CMN PLL device node Luo Jie
2026-07-24 15:00 ` [PATCH 12/12] arm64: dts: qcom: Update IPQ5210 xo_board to use fixed factor clock Luo Jie
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