[PATCH 0/2] x86: KVM: Add missing AMD features

[PATCH 0/2] x86: KVM: Add missing AMD features

[Maksim Davydov]

This series adds definition of some missing AMD features in
0x80000008_EBX and 0x80000021_EAX functions. It also gives an opportunity
to expose these features to userspace. 

Related discussion in QEMU:
https://lore.kernel.org/kvm/24462567-e486-4b7f-b869-a1fab48d739c@yandex-team.ru/

Maksim Davydov (2):
  x86: KVM: Advertise FSRS and FSRC on AMD to userspace
  x86: KVM: Advertise AMD's speculation control features

 arch/x86/include/asm/cpufeatures.h | 5 +++++
 arch/x86/kvm/cpuid.c               | 9 +++++----
 2 files changed, 10 insertions(+), 4 deletions(-)

-- 
2.34.1

[PATCH 1/2] x86: KVM: Advertise FSRS and FSRC on AMD to userspace

[Maksim Davydov]

Fast short REP STOSB and fast short CMPSB support on AMD processors are
provided in other CPUID function in comparison with Intel processors:
* FSRS: 10 bit in 0x80000021_EAX
* FSRC: 11 bit in 0x80000021_EAX

AMD bit numbers differ from existing definition of FSRC and
FSRS. So, the new appropriate values have to be added with new names.

It's safe to advertise these features to userspace because they are a part
of CPU model definition and they can't be disabled (as existing Intel
features).

Fixes: 2a4209d6a9cb ("KVM: x86: Advertise fast REP string features inherent to the CPU")
Signed-off-by: Maksim Davydov <davydov-max@yandex-team.ru>
---
 arch/x86/include/asm/cpufeatures.h | 2 ++
 arch/x86/kvm/cpuid.c               | 4 ++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 913fd3a7bac6..2f8a858325a4 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -457,6 +457,8 @@
 #define X86_FEATURE_NULL_SEL_CLR_BASE	(20*32+ 6) /* Null Selector Clears Base */
 #define X86_FEATURE_AUTOIBRS		(20*32+ 8) /* Automatic IBRS */
 #define X86_FEATURE_NO_SMM_CTL_MSR	(20*32+ 9) /* SMM_CTL MSR is not present */
+#define X86_FEATURE_AMD_FSRS	        (20*32+10) /* AMD Fast short REP STOSB supported */
+#define X86_FEATURE_AMD_FSRC		(20*30+11) /* AMD Fast short REP CMPSB supported */
 
 #define X86_FEATURE_SBPB		(20*32+27) /* Selective Branch Prediction Barrier */
 #define X86_FEATURE_IBPB_BRTYPE		(20*32+28) /* MSR_PRED_CMD[IBPB] flushes all branch type predictions */
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 41786b834b16..30ce1bcfc47f 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -793,8 +793,8 @@ void kvm_set_cpu_caps(void)
 
 	kvm_cpu_cap_mask(CPUID_8000_0021_EAX,
 		F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ |
-		F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ |
-		F(WRMSR_XX_BASE_NS)
+		F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | F(AMD_FSRS) |
+		F(AMD_FSRC) | 0 /* PrefetchCtlMsr */ | F(WRMSR_XX_BASE_NS)
 	);
 
 	kvm_cpu_cap_check_and_set(X86_FEATURE_SBPB);
-- 
2.34.1

Re: [PATCH 1/2] x86: KVM: Advertise FSRS and FSRC on AMD to userspace

[Moger, Babu]

Hi Maksim,

On 11/13/2024 7:30 AM, Maksim Davydov wrote:
> Fast short REP STOSB and fast short CMPSB support on AMD processors are
> provided in other CPUID function in comparison with Intel processors:
> * FSRS: 10 bit in 0x80000021_EAX
> * FSRC: 11 bit in 0x80000021_EAX
> 
> AMD bit numbers differ from existing definition of FSRC and
> FSRS. So, the new appropriate values have to be added with new names.
> 
> It's safe to advertise these features to userspace because they are a part
> of CPU model definition and they can't be disabled (as existing Intel
> features).
> 
> Fixes: 2a4209d6a9cb ("KVM: x86: Advertise fast REP string features inherent to the CPU")
> Signed-off-by: Maksim Davydov <davydov-max@yandex-team.ru>
> ---
>   arch/x86/include/asm/cpufeatures.h | 2 ++
>   arch/x86/kvm/cpuid.c               | 4 ++--
>   2 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 913fd3a7bac6..2f8a858325a4 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -457,6 +457,8 @@
>   #define X86_FEATURE_NULL_SEL_CLR_BASE	(20*32+ 6) /* Null Selector Clears Base */
>   #define X86_FEATURE_AUTOIBRS		(20*32+ 8) /* Automatic IBRS */
>   #define X86_FEATURE_NO_SMM_CTL_MSR	(20*32+ 9) /* SMM_CTL MSR is not present */
> +#define X86_FEATURE_AMD_FSRS	        (20*32+10) /* AMD Fast short REP STOSB supported */
> +#define X86_FEATURE_AMD_FSRC		(20*30+11) /* AMD Fast short REP CMPSB supported */
>   
>   #define X86_FEATURE_SBPB		(20*32+27) /* Selective Branch Prediction Barrier */
>   #define X86_FEATURE_IBPB_BRTYPE		(20*32+28) /* MSR_PRED_CMD[IBPB] flushes all branch type predictions */
> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> index 41786b834b16..30ce1bcfc47f 100644
> --- a/arch/x86/kvm/cpuid.c
> +++ b/arch/x86/kvm/cpuid.c
> @@ -793,8 +793,8 @@ void kvm_set_cpu_caps(void)
>   
>   	kvm_cpu_cap_mask(CPUID_8000_0021_EAX,
>   		F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ |
> -		F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ |
> -		F(WRMSR_XX_BASE_NS)
> +		F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | F(AMD_FSRS) |
> +		F(AMD_FSRC) | 0 /* PrefetchCtlMsr */ | F(WRMSR_XX_BASE_NS)

KVM still does not report AMD_FSRC.

The KVM_GET_SUPPORTED_CPUID output for the function 0x80000021.

{0x80000021, 0000, eax = 0x1800074f, ebx= 0000000000, ecx = 0000000000, 
edx= 0000000000}, /* 0 */



>   	);
>   
>   	kvm_cpu_cap_check_and_set(X86_FEATURE_SBPB);

-- 
- Babu Moger

Re: [PATCH 1/2] x86: KVM: Advertise FSRS and FSRC on AMD to userspace

[Maksim Davydov]

Hi!

On 11/15/24 22:51, Moger, Babu wrote:
> Hi Maksim,
> 
> On 11/13/2024 7:30 AM, Maksim Davydov wrote:
>> Fast short REP STOSB and fast short CMPSB support on AMD processors are
>> provided in other CPUID function in comparison with Intel processors:
>> * FSRS: 10 bit in 0x80000021_EAX
>> * FSRC: 11 bit in 0x80000021_EAX
>>
>> AMD bit numbers differ from existing definition of FSRC and
>> FSRS. So, the new appropriate values have to be added with new names.
>>
>> It's safe to advertise these features to userspace because they are a 
>> part
>> of CPU model definition and they can't be disabled (as existing Intel
>> features).
>>
>> Fixes: 2a4209d6a9cb ("KVM: x86: Advertise fast REP string features 
>> inherent to the CPU")
>> Signed-off-by: Maksim Davydov <davydov-max@yandex-team.ru>
>> ---
>>   arch/x86/include/asm/cpufeatures.h | 2 ++
>>   arch/x86/kvm/cpuid.c               | 4 ++--
>>   2 files changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/x86/include/asm/cpufeatures.h 
>> b/arch/x86/include/asm/cpufeatures.h
>> index 913fd3a7bac6..2f8a858325a4 100644
>> --- a/arch/x86/include/asm/cpufeatures.h
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -457,6 +457,8 @@
>>   #define X86_FEATURE_NULL_SEL_CLR_BASE    (20*32+ 6) /* Null Selector 
>> Clears Base */
>>   #define X86_FEATURE_AUTOIBRS        (20*32+ 8) /* Automatic IBRS */
>>   #define X86_FEATURE_NO_SMM_CTL_MSR    (20*32+ 9) /* SMM_CTL MSR is 
>> not present */
>> +#define X86_FEATURE_AMD_FSRS            (20*32+10) /* AMD Fast short 
>> REP STOSB supported */
>> +#define X86_FEATURE_AMD_FSRC        (20*30+11) /* AMD Fast short REP 

Sorry
I made a mistake (30 instead of 32) while preparing the patch.
I'll prepare the new version.

>> CMPSB supported */
>>   #define X86_FEATURE_SBPB        (20*32+27) /* Selective Branch 
>> Prediction Barrier */
>>   #define X86_FEATURE_IBPB_BRTYPE        (20*32+28) /* 
>> MSR_PRED_CMD[IBPB] flushes all branch type predictions */
>> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
>> index 41786b834b16..30ce1bcfc47f 100644
>> --- a/arch/x86/kvm/cpuid.c
>> +++ b/arch/x86/kvm/cpuid.c
>> @@ -793,8 +793,8 @@ void kvm_set_cpu_caps(void)
>>       kvm_cpu_cap_mask(CPUID_8000_0021_EAX,
>>           F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ |
>> -        F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ |
>> -        F(WRMSR_XX_BASE_NS)
>> +        F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | F(AMD_FSRS) |
>> +        F(AMD_FSRC) | 0 /* PrefetchCtlMsr */ | F(WRMSR_XX_BASE_NS)
> 
> KVM still does not report AMD_FSRC.
> 
> The KVM_GET_SUPPORTED_CPUID output for the function 0x80000021.
> 
> {0x80000021, 0000, eax = 0x1800074f, ebx= 0000000000, ecx = 0000000000, 
> edx= 0000000000}, /* 0 */
> 
> 
> 
>>       );
>>       kvm_cpu_cap_check_and_set(X86_FEATURE_SBPB);
> 

-- 
Best regards,
Maksim Davydov

[PATCH 2/2] x86: KVM: Advertise AMD's speculation control features

[Maksim Davydov]

It seems helpful to expose to userspace some speculation control features
from 0x80000008_EBX function:
* 16 bit. IBRS always on. Indicates whether processor prefers that
  IBRS is always on. It simplifies speculation managing.
* 18 bit. IBRS is preferred over software solution. Indicates that
  software mitigations can be replaced with more performant IBRS.
* 19 bit. IBRS provides Same Mode Protection. Indicates that when IBRS
  is set indirect branch predictions are not influenced by any prior
  indirect branches.
* 29 bit. BTC_NO. Indicates that processor isn't affected by branch type
  confusion. It's used during mitigations setting up.
* 30 bit. IBPB clears return address predictor. It's used during
  mitigations setting up.

Signed-off-by: Maksim Davydov <davydov-max@yandex-team.ru>
---
 arch/x86/include/asm/cpufeatures.h | 3 +++
 arch/x86/kvm/cpuid.c               | 5 +++--
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 2f8a858325a4..f5491bba75fc 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -340,7 +340,10 @@
 #define X86_FEATURE_AMD_IBPB		(13*32+12) /* Indirect Branch Prediction Barrier */
 #define X86_FEATURE_AMD_IBRS		(13*32+14) /* Indirect Branch Restricted Speculation */
 #define X86_FEATURE_AMD_STIBP		(13*32+15) /* Single Thread Indirect Branch Predictors */
+#define X86_FEATURE_AMD_IBRS_ALWAYS_ON	(13*32+16) /* Indirect Branch Restricted Speculation always-on preferred */
 #define X86_FEATURE_AMD_STIBP_ALWAYS_ON	(13*32+17) /* Single Thread Indirect Branch Predictors always-on preferred */
+#define X86_FEATURE_AMD_IBRS_PREFERRED	(13*32+18) /* Indirect Branch Restricted Speculation is preferred over SW solution */
+#define X86_FEATURE_AMD_IBRS_SMP	(13*32+19) /* Indirect Branch Restricted Speculation provides Same Mode Protection */
 #define X86_FEATURE_AMD_PPIN		(13*32+23) /* "amd_ppin" Protected Processor Inventory Number */
 #define X86_FEATURE_AMD_SSBD		(13*32+24) /* Speculative Store Bypass Disable */
 #define X86_FEATURE_VIRT_SSBD		(13*32+25) /* "virt_ssbd" Virtualized Speculative Store Bypass Disable */
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 30ce1bcfc47f..5b2d52913b18 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -754,8 +754,9 @@ void kvm_set_cpu_caps(void)
 	kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
 		F(CLZERO) | F(XSAVEERPTR) |
 		F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
-		F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) |
-		F(AMD_PSFD)
+		F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_IBRS_ALWAYS_ON) |
+		F(AMD_STIBP_ALWAYS_ON) | F(AMD_IBRS_PREFERRED) |
+		F(AMD_IBRS_SMP) | F(AMD_PSFD) | F(BTC_NO) | F(AMD_IBPB_RET)
 	);
 
 	/*
-- 
2.34.1

Re: [PATCH 2/2] x86: KVM: Advertise AMD's speculation control features

[Moger, Babu]

Hi Maksim,


On 11/13/2024 7:30 AM, Maksim Davydov wrote:
> It seems helpful to expose to userspace some speculation control features
> from 0x80000008_EBX function:
> * 16 bit. IBRS always on. Indicates whether processor prefers that
>    IBRS is always on. It simplifies speculation managing.

Spec say bit 16 is reserved.

16 Reserved

https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip

> * 18 bit. IBRS is preferred over software solution. Indicates that
>    software mitigations can be replaced with more performant IBRS.
> * 19 bit. IBRS provides Same Mode Protection. Indicates that when IBRS
>    is set indirect branch predictions are not influenced by any prior
>    indirect branches.
> * 29 bit. BTC_NO. Indicates that processor isn't affected by branch type
>    confusion. It's used during mitigations setting up.
> * 30 bit. IBPB clears return address predictor. It's used during
>    mitigations setting up.
> 
> Signed-off-by: Maksim Davydov <davydov-max@yandex-team.ru>
> ---
>   arch/x86/include/asm/cpufeatures.h | 3 +++
>   arch/x86/kvm/cpuid.c               | 5 +++--
>   2 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 2f8a858325a4..f5491bba75fc 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -340,7 +340,10 @@
>   #define X86_FEATURE_AMD_IBPB		(13*32+12) /* Indirect Branch Prediction Barrier */
>   #define X86_FEATURE_AMD_IBRS		(13*32+14) /* Indirect Branch Restricted Speculation */
>   #define X86_FEATURE_AMD_STIBP		(13*32+15) /* Single Thread Indirect Branch Predictors */
> +#define X86_FEATURE_AMD_IBRS_ALWAYS_ON	(13*32+16) /* Indirect Branch Restricted Speculation always-on preferred */

You might have to remove this.

>   #define X86_FEATURE_AMD_STIBP_ALWAYS_ON	(13*32+17) /* Single Thread Indirect Branch Predictors always-on preferred */
> +#define X86_FEATURE_AMD_IBRS_PREFERRED	(13*32+18) /* Indirect Branch Restricted Speculation is preferred over SW solution */
> +#define X86_FEATURE_AMD_IBRS_SMP	(13*32+19) /* Indirect Branch Restricted Speculation provides Same Mode Protection */
>   #define X86_FEATURE_AMD_PPIN		(13*32+23) /* "amd_ppin" Protected Processor Inventory Number */
>   #define X86_FEATURE_AMD_SSBD		(13*32+24) /* Speculative Store Bypass Disable */
>   #define X86_FEATURE_VIRT_SSBD		(13*32+25) /* "virt_ssbd" Virtualized Speculative Store Bypass Disable */
> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> index 30ce1bcfc47f..5b2d52913b18 100644
> --- a/arch/x86/kvm/cpuid.c
> +++ b/arch/x86/kvm/cpuid.c
> @@ -754,8 +754,9 @@ void kvm_set_cpu_caps(void)
>   	kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
>   		F(CLZERO) | F(XSAVEERPTR) |
>   		F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
> -		F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) |
> -		F(AMD_PSFD)
> +		F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_IBRS_ALWAYS_ON) |
> +		F(AMD_STIBP_ALWAYS_ON) | F(AMD_IBRS_PREFERRED) |
> +		F(AMD_IBRS_SMP) | F(AMD_PSFD) | F(BTC_NO) | F(AMD_IBPB_RET)
>   	);
>   
>   	/*

-- 
- Babu Moger

Re: [PATCH 2/2] x86: KVM: Advertise AMD's speculation control features

[Jim Mattson]

On Fri, Nov 15, 2024 at 12:13 PM Moger, Babu <bmoger@amd.com> wrote:
>
> Hi Maksim,
>
>
> On 11/13/2024 7:30 AM, Maksim Davydov wrote:
> > It seems helpful to expose to userspace some speculation control features
> > from 0x80000008_EBX function:
> > * 16 bit. IBRS always on. Indicates whether processor prefers that
> >    IBRS is always on. It simplifies speculation managing.
>
> Spec say bit 16 is reserved.
>
> 16 Reserved
>
> https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip

The APM volume 3 ( 24594—Rev. 3.36—March 2024) declares this bit as
"Processor prefers that STIBP be left on." Once a bit has been
documented like that, you have to assume that software has been
written that expects those semantics. AMD does not have the option of
undocumenting the bit.  You can deprecate it, but it now has the
originally documented semantics until the end of time.

> > * 18 bit. IBRS is preferred over software solution. Indicates that
> >    software mitigations can be replaced with more performant IBRS.
> > * 19 bit. IBRS provides Same Mode Protection. Indicates that when IBRS
> >    is set indirect branch predictions are not influenced by any prior
> >    indirect branches.
> > * 29 bit. BTC_NO. Indicates that processor isn't affected by branch type
> >    confusion. It's used during mitigations setting up.
> > * 30 bit. IBPB clears return address predictor. It's used during
> >    mitigations setting up.
> >
> > Signed-off-by: Maksim Davydov <davydov-max@yandex-team.ru>
> > ---
> >   arch/x86/include/asm/cpufeatures.h | 3 +++
> >   arch/x86/kvm/cpuid.c               | 5 +++--
> >   2 files changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> > index 2f8a858325a4..f5491bba75fc 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -340,7 +340,10 @@
> >   #define X86_FEATURE_AMD_IBPB                (13*32+12) /* Indirect Branch Prediction Barrier */
> >   #define X86_FEATURE_AMD_IBRS                (13*32+14) /* Indirect Branch Restricted Speculation */
> >   #define X86_FEATURE_AMD_STIBP               (13*32+15) /* Single Thread Indirect Branch Predictors */
> > +#define X86_FEATURE_AMD_IBRS_ALWAYS_ON       (13*32+16) /* Indirect Branch Restricted Speculation always-on preferred */
>
> You might have to remove this.

No; it's fine. The bit can never be used for anything else.

> >   #define X86_FEATURE_AMD_STIBP_ALWAYS_ON     (13*32+17) /* Single Thread Indirect Branch Predictors always-on preferred */
> > +#define X86_FEATURE_AMD_IBRS_PREFERRED       (13*32+18) /* Indirect Branch Restricted Speculation is preferred over SW solution */
> > +#define X86_FEATURE_AMD_IBRS_SMP     (13*32+19) /* Indirect Branch Restricted Speculation provides Same Mode Protection */
> >   #define X86_FEATURE_AMD_PPIN                (13*32+23) /* "amd_ppin" Protected Processor Inventory Number */
> >   #define X86_FEATURE_AMD_SSBD                (13*32+24) /* Speculative Store Bypass Disable */
> >   #define X86_FEATURE_VIRT_SSBD               (13*32+25) /* "virt_ssbd" Virtualized Speculative Store Bypass Disable */
> > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> > index 30ce1bcfc47f..5b2d52913b18 100644
> > --- a/arch/x86/kvm/cpuid.c
> > +++ b/arch/x86/kvm/cpuid.c
> > @@ -754,8 +754,9 @@ void kvm_set_cpu_caps(void)
> >       kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
> >               F(CLZERO) | F(XSAVEERPTR) |
> >               F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
> > -             F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) |
> > -             F(AMD_PSFD)
> > +             F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_IBRS_ALWAYS_ON) |
> > +             F(AMD_STIBP_ALWAYS_ON) | F(AMD_IBRS_PREFERRED) |
> > +             F(AMD_IBRS_SMP) | F(AMD_PSFD) | F(BTC_NO) | F(AMD_IBPB_RET)
> >       );
> >
> >       /*
>
> --
> - Babu Moger
>

Re: [PATCH 2/2] x86: KVM: Advertise AMD's speculation control features

[Moger, Babu]

On 11/15/2024 2:32 PM, Jim Mattson wrote:
> On Fri, Nov 15, 2024 at 12:13 PM Moger, Babu <bmoger@amd.com> wrote:
>>
>> Hi Maksim,
>>
>>
>> On 11/13/2024 7:30 AM, Maksim Davydov wrote:
>>> It seems helpful to expose to userspace some speculation control features
>>> from 0x80000008_EBX function:
>>> * 16 bit. IBRS always on. Indicates whether processor prefers that
>>>     IBRS is always on. It simplifies speculation managing.
>>
>> Spec say bit 16 is reserved.
>>
>> 16 Reserved
>>
>> https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip
> 
> The APM volume 3 ( 24594—Rev. 3.36—March 2024) declares this bit as
> "Processor prefers that STIBP be left on." Once a bit has been
> documented like that, you have to assume that software has been
> written that expects those semantics. AMD does not have the option of
> undocumenting the bit.  You can deprecate it, but it now has the
> originally documented semantics until the end of time.

Yes. Agreed.

> 
>>> * 18 bit. IBRS is preferred over software solution. Indicates that
>>>     software mitigations can be replaced with more performant IBRS.
>>> * 19 bit. IBRS provides Same Mode Protection. Indicates that when IBRS
>>>     is set indirect branch predictions are not influenced by any prior
>>>     indirect branches.
>>> * 29 bit. BTC_NO. Indicates that processor isn't affected by branch type
>>>     confusion. It's used during mitigations setting up.
>>> * 30 bit. IBPB clears return address predictor. It's used during
>>>     mitigations setting up.
>>>
>>> Signed-off-by: Maksim Davydov <davydov-max@yandex-team.ru>
>>> ---
>>>    arch/x86/include/asm/cpufeatures.h | 3 +++
>>>    arch/x86/kvm/cpuid.c               | 5 +++--
>>>    2 files changed, 6 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
>>> index 2f8a858325a4..f5491bba75fc 100644
>>> --- a/arch/x86/include/asm/cpufeatures.h
>>> +++ b/arch/x86/include/asm/cpufeatures.h
>>> @@ -340,7 +340,10 @@
>>>    #define X86_FEATURE_AMD_IBPB                (13*32+12) /* Indirect Branch Prediction Barrier */
>>>    #define X86_FEATURE_AMD_IBRS                (13*32+14) /* Indirect Branch Restricted Speculation */
>>>    #define X86_FEATURE_AMD_STIBP               (13*32+15) /* Single Thread Indirect Branch Predictors */
>>> +#define X86_FEATURE_AMD_IBRS_ALWAYS_ON       (13*32+16) /* Indirect Branch Restricted Speculation always-on preferred */
>>
>> You might have to remove this.
> 
> No; it's fine. The bit can never be used for anything else.

That is true.
But, Hardware does not report this bit yet (at least on my system). So, 
I am thinking it may not be required to add at this point.

> 
>>>    #define X86_FEATURE_AMD_STIBP_ALWAYS_ON     (13*32+17) /* Single Thread Indirect Branch Predictors always-on preferred */
>>> +#define X86_FEATURE_AMD_IBRS_PREFERRED       (13*32+18) /* Indirect Branch Restricted Speculation is preferred over SW solution */
>>> +#define X86_FEATURE_AMD_IBRS_SMP     (13*32+19) /* Indirect Branch Restricted Speculation provides Same Mode Protection */
>>>    #define X86_FEATURE_AMD_PPIN                (13*32+23) /* "amd_ppin" Protected Processor Inventory Number */
>>>    #define X86_FEATURE_AMD_SSBD                (13*32+24) /* Speculative Store Bypass Disable */
>>>    #define X86_FEATURE_VIRT_SSBD               (13*32+25) /* "virt_ssbd" Virtualized Speculative Store Bypass Disable */
>>> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
>>> index 30ce1bcfc47f..5b2d52913b18 100644
>>> --- a/arch/x86/kvm/cpuid.c
>>> +++ b/arch/x86/kvm/cpuid.c
>>> @@ -754,8 +754,9 @@ void kvm_set_cpu_caps(void)
>>>        kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
>>>                F(CLZERO) | F(XSAVEERPTR) |
>>>                F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
>>> -             F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) |
>>> -             F(AMD_PSFD)
>>> +             F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_IBRS_ALWAYS_ON) |
>>> +             F(AMD_STIBP_ALWAYS_ON) | F(AMD_IBRS_PREFERRED) |
>>> +             F(AMD_IBRS_SMP) | F(AMD_PSFD) | F(BTC_NO) | F(AMD_IBPB_RET)
>>>        );
>>>
>>>        /*
>>
>> --
>> - Babu Moger
>>
> 

-- 
- Babu Moger

Re: [PATCH 2/2] x86: KVM: Advertise AMD's speculation control features

[Maksim Davydov]

Hi!

On 11/16/24 00:29, Moger, Babu wrote:
> 
> 
> On 11/15/2024 2:32 PM, Jim Mattson wrote:
>> On Fri, Nov 15, 2024 at 12:13 PM Moger, Babu <bmoger@amd.com> wrote:
>>>
>>> Hi Maksim,
>>>
>>>
>>> On 11/13/2024 7:30 AM, Maksim Davydov wrote:
>>>> It seems helpful to expose to userspace some speculation control 
>>>> features
>>>> from 0x80000008_EBX function:
>>>> * 16 bit. IBRS always on. Indicates whether processor prefers that
>>>>     IBRS is always on. It simplifies speculation managing.
>>>
>>> Spec say bit 16 is reserved.
>>>
>>> 16 Reserved
>>>
>>> https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip
>>
>> The APM volume 3 ( 24594—Rev. 3.36—March 2024) declares this bit as
>> "Processor prefers that STIBP be left on." Once a bit has been
>> documented like that, you have to assume that software has been
>> written that expects those semantics. AMD does not have the option of
>> undocumenting the bit.  You can deprecate it, but it now has the
>> originally documented semantics until the end of time.
> 
> Yes. Agreed.
> 
>>
>>>> * 18 bit. IBRS is preferred over software solution. Indicates that
>>>>     software mitigations can be replaced with more performant IBRS.
>>>> * 19 bit. IBRS provides Same Mode Protection. Indicates that when IBRS
>>>>     is set indirect branch predictions are not influenced by any prior
>>>>     indirect branches.
>>>> * 29 bit. BTC_NO. Indicates that processor isn't affected by branch 
>>>> type
>>>>     confusion. It's used during mitigations setting up.
>>>> * 30 bit. IBPB clears return address predictor. It's used during
>>>>     mitigations setting up.
>>>>
>>>> Signed-off-by: Maksim Davydov <davydov-max@yandex-team.ru>
>>>> ---
>>>>    arch/x86/include/asm/cpufeatures.h | 3 +++
>>>>    arch/x86/kvm/cpuid.c               | 5 +++--
>>>>    2 files changed, 6 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/x86/include/asm/cpufeatures.h 
>>>> b/arch/x86/include/asm/cpufeatures.h
>>>> index 2f8a858325a4..f5491bba75fc 100644
>>>> --- a/arch/x86/include/asm/cpufeatures.h
>>>> +++ b/arch/x86/include/asm/cpufeatures.h
>>>> @@ -340,7 +340,10 @@
>>>>    #define X86_FEATURE_AMD_IBPB                (13*32+12) /* 
>>>> Indirect Branch Prediction Barrier */
>>>>    #define X86_FEATURE_AMD_IBRS                (13*32+14) /* 
>>>> Indirect Branch Restricted Speculation */
>>>>    #define X86_FEATURE_AMD_STIBP               (13*32+15) /* Single 
>>>> Thread Indirect Branch Predictors */
>>>> +#define X86_FEATURE_AMD_IBRS_ALWAYS_ON       (13*32+16) /* Indirect 
>>>> Branch Restricted Speculation always-on preferred */
>>>
>>> You might have to remove this.
>>
>> No; it's fine. The bit can never be used for anything else.
> 
> That is true.
> But, Hardware does not report this bit yet (at least on my system). So, 
> I am thinking it may not be required to add at this point.
> 

Yes, I used information about bits from "AMD64 Architecture Programmer’s 
Manual". So I thought, if the bit is defined in this manual, it can be 
used in any processor.
I've checked PPRs for EPYC Rome, Milan and Genoa and the 16 bit is 
reserved for all of these processors. But I don't know if there are any 
other processors with the 16 bit set.

>>
>>>>    #define X86_FEATURE_AMD_STIBP_ALWAYS_ON     (13*32+17) /* Single 
>>>> Thread Indirect Branch Predictors always-on preferred */
>>>> +#define X86_FEATURE_AMD_IBRS_PREFERRED       (13*32+18) /* Indirect 
>>>> Branch Restricted Speculation is preferred over SW solution */
>>>> +#define X86_FEATURE_AMD_IBRS_SMP     (13*32+19) /* Indirect Branch 
>>>> Restricted Speculation provides Same Mode Protection */
>>>>    #define X86_FEATURE_AMD_PPIN                (13*32+23) /* 
>>>> "amd_ppin" Protected Processor Inventory Number */
>>>>    #define X86_FEATURE_AMD_SSBD                (13*32+24) /* 
>>>> Speculative Store Bypass Disable */
>>>>    #define X86_FEATURE_VIRT_SSBD               (13*32+25) /* 
>>>> "virt_ssbd" Virtualized Speculative Store Bypass Disable */
>>>> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
>>>> index 30ce1bcfc47f..5b2d52913b18 100644
>>>> --- a/arch/x86/kvm/cpuid.c
>>>> +++ b/arch/x86/kvm/cpuid.c
>>>> @@ -754,8 +754,9 @@ void kvm_set_cpu_caps(void)
>>>>        kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
>>>>                F(CLZERO) | F(XSAVEERPTR) |
>>>>                F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) 
>>>> | F(VIRT_SSBD) |
>>>> -             F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) |
>>>> -             F(AMD_PSFD)
>>>> +             F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_IBRS_ALWAYS_ON) |
>>>> +             F(AMD_STIBP_ALWAYS_ON) | F(AMD_IBRS_PREFERRED) |
>>>> +             F(AMD_IBRS_SMP) | F(AMD_PSFD) | F(BTC_NO) | 
>>>> F(AMD_IBPB_RET)
>>>>        );
>>>>
>>>>        /*
>>>
>>> -- 
>>> - Babu Moger
>>>
>>
> 

-- 
Best regards,
Maksim Davydov

Re: [PATCH 2/2] x86: KVM: Advertise AMD's speculation control features

[Tom Lendacky]

On 11/15/24 14:32, Jim Mattson wrote:
> On Fri, Nov 15, 2024 at 12:13 PM Moger, Babu <bmoger@amd.com> wrote:
>>
>> Hi Maksim,
>>
>>
>> On 11/13/2024 7:30 AM, Maksim Davydov wrote:
>>> It seems helpful to expose to userspace some speculation control features
>>> from 0x80000008_EBX function:
>>> * 16 bit. IBRS always on. Indicates whether processor prefers that
>>>    IBRS is always on. It simplifies speculation managing.
>>
>> Spec say bit 16 is reserved.
>>
>> 16 Reserved
>>
>> https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip
> 
> The APM volume 3 ( 24594—Rev. 3.36—March 2024) declares this bit as
> "Processor prefers that STIBP be left on." Once a bit has been
> documented like that, you have to assume that software has been
> written that expects those semantics. AMD does not have the option of
> undocumenting the bit.  You can deprecate it, but it now has the
> originally documented semantics until the end of time.

Just for accuracy, the APM version referred to has bit 16 declared as
"Processor prefers that IBRS be left on.", not STIBP.

Thanks,
Tom

> 
>>> * 18 bit. IBRS is preferred over software solution. Indicates that
>>>    software mitigations can be replaced with more performant IBRS.
>>> * 19 bit. IBRS provides Same Mode Protection. Indicates that when IBRS
>>>    is set indirect branch predictions are not influenced by any prior
>>>    indirect branches.
>>> * 29 bit. BTC_NO. Indicates that processor isn't affected by branch type
>>>    confusion. It's used during mitigations setting up.
>>> * 30 bit. IBPB clears return address predictor. It's used during
>>>    mitigations setting up.
>>>
>>> Signed-off-by: Maksim Davydov <davydov-max@yandex-team.ru>
>>> ---
>>>   arch/x86/include/asm/cpufeatures.h | 3 +++
>>>   arch/x86/kvm/cpuid.c               | 5 +++--
>>>   2 files changed, 6 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
>>> index 2f8a858325a4..f5491bba75fc 100644
>>> --- a/arch/x86/include/asm/cpufeatures.h
>>> +++ b/arch/x86/include/asm/cpufeatures.h
>>> @@ -340,7 +340,10 @@
>>>   #define X86_FEATURE_AMD_IBPB                (13*32+12) /* Indirect Branch Prediction Barrier */
>>>   #define X86_FEATURE_AMD_IBRS                (13*32+14) /* Indirect Branch Restricted Speculation */
>>>   #define X86_FEATURE_AMD_STIBP               (13*32+15) /* Single Thread Indirect Branch Predictors */
>>> +#define X86_FEATURE_AMD_IBRS_ALWAYS_ON       (13*32+16) /* Indirect Branch Restricted Speculation always-on preferred */
>>
>> You might have to remove this.
> 
> No; it's fine. The bit can never be used for anything else.
> 
>>>   #define X86_FEATURE_AMD_STIBP_ALWAYS_ON     (13*32+17) /* Single Thread Indirect Branch Predictors always-on preferred */
>>> +#define X86_FEATURE_AMD_IBRS_PREFERRED       (13*32+18) /* Indirect Branch Restricted Speculation is preferred over SW solution */
>>> +#define X86_FEATURE_AMD_IBRS_SMP     (13*32+19) /* Indirect Branch Restricted Speculation provides Same Mode Protection */
>>>   #define X86_FEATURE_AMD_PPIN                (13*32+23) /* "amd_ppin" Protected Processor Inventory Number */
>>>   #define X86_FEATURE_AMD_SSBD                (13*32+24) /* Speculative Store Bypass Disable */
>>>   #define X86_FEATURE_VIRT_SSBD               (13*32+25) /* "virt_ssbd" Virtualized Speculative Store Bypass Disable */
>>> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
>>> index 30ce1bcfc47f..5b2d52913b18 100644
>>> --- a/arch/x86/kvm/cpuid.c
>>> +++ b/arch/x86/kvm/cpuid.c
>>> @@ -754,8 +754,9 @@ void kvm_set_cpu_caps(void)
>>>       kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
>>>               F(CLZERO) | F(XSAVEERPTR) |
>>>               F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
>>> -             F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) |
>>> -             F(AMD_PSFD)
>>> +             F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_IBRS_ALWAYS_ON) |
>>> +             F(AMD_STIBP_ALWAYS_ON) | F(AMD_IBRS_PREFERRED) |
>>> +             F(AMD_IBRS_SMP) | F(AMD_PSFD) | F(BTC_NO) | F(AMD_IBPB_RET)
>>>       );
>>>
>>>       /*
>>
>> --
>> - Babu Moger
>>
> 

Re: [PATCH 0/2] x86: KVM: Add missing AMD features

[Borislav Petkov]

On Wed, Nov 13, 2024 at 04:30:40PM +0300, Maksim Davydov wrote:
> This series adds definition of some missing AMD features in
> 0x80000008_EBX and 0x80000021_EAX functions. It also gives an opportunity
> to expose these features to userspace.

Any particular, concrete use for them in luserspace or this is a just-for-fun
exercise?

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH 0/2] x86: KVM: Add missing AMD features

[Maksim Davydov]

Hi!

On 11/16/24 14:47, Borislav Petkov wrote:
> On Wed, Nov 13, 2024 at 04:30:40PM +0300, Maksim Davydov wrote:
>> This series adds definition of some missing AMD features in
>> 0x80000008_EBX and 0x80000021_EAX functions. It also gives an opportunity
>> to expose these features to userspace.
> 
> Any particular, concrete use for them in luserspace or this is a just-for-fun
> exercise?
> 

Yes, BTC_NO and AMD_IBPB_RET are used by guests while choosing mitigations.

-- 
Best regards,
Maksim Davydov

Re: [PATCH 0/2] x86: KVM: Add missing AMD features

[Borislav Petkov]

On Sat, Nov 16, 2024 at 03:02:47PM +0300, Maksim Davydov wrote:
> Yes, BTC_NO and AMD_IBPB_RET are used by guests while choosing mitigations.

How?

Basically what the current code does to do retbleed or IBPB on entry? Where
latter means the HV allows writes to MSR_IA32_PRED_CMD...?

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH 0/2] x86: KVM: Add missing AMD features

[Maksim Davydov]

On 11/16/24 15:10, Borislav Petkov wrote:
> On Sat, Nov 16, 2024 at 03:02:47PM +0300, Maksim Davydov wrote:
>> Yes, BTC_NO and AMD_IBPB_RET are used by guests while choosing mitigations.
> 
> How?
> 
> Basically what the current code does to do retbleed or IBPB on entry? Where
> latter means the HV allows writes to MSR_IA32_PRED_CMD...?
>

Not sure If I understood your question correctly, but I meant these two 
examples:
* BTC_NO. For instance, we want to create Zen2 (family 17h) guest on 
host with Zen4 (family 19h) processor. If guest doesn't have 
X86_FEATURE_BTC_NO, blacklist will be used to determine whether CPU 
model is vulnerable to retbleed or not. 17h family is in the blacklist. 
So, the guest will use "untrained return thunk" or another retbleed 
mitigation. But we can expose to the guest that host processor (family 
19h) isn't vulnerable to rebleed and improve guest performance without 
any security risks
* AMD_IBPB_RET. On AMD we can pass through MSR_IA32_PRED_CMD. So, the 
guest can use IBPB on entry to mitigate SRSO (instead of the default 
mitigation). In this case I don't see any problems, because KVM allows 
writes to MSR_IA32_PRED_CMD. But AMD_IBPB_RET is used to determine the 
appropriate stub in end of entry_ibpb. Without exposing AMD_IBPB_RET, 
the guest will use stronger mitigation.

I don't have access to Zen4 host now, but it seems that both of these 
cases can have an impact on performance. I can try to measure this 
impact later if needed.

-- 
Best regards,
Maksim Davydov