Question about cacheline aligned memory for DMA transfers

[Johannes Thoma <johannes@johannesthoma.com>]

Dear list,

I am working on a memory corruption problem with a patched 2.6.21 kernel in the
USB driver. In order to better understand the problem I would like to ask how
current kernels handle the case where the same cacheline is used for a DMA-able
object and another object.

Does kmalloc return only memory that is cache line aligned? If not, do all
architectures handle cache line misalign
ed dma accesses correctly like the powerpc (although not yet in 2.6.21)
architecture does?

Thanks for any insights.

- Johannes

PS: Please CC me I am not on the list.